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AM4376 Datasheet(PDF) 224 Page - Texas Instruments

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Part # AM4376
Description  AM437x Sitara??Processors
PDF  261 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AM4376 Datasheet(HTML) 224 Page - Texas Instruments

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AM4376, AM4377, AM4378, AM4379
SPRS851B – JUNE 2014 – REVISED APRIL 2015
www.ti.com
5.12.13 Multichannel Serial Port Interface (McSPI)
For more information, see the Multichannel Serial Port Interface (McSPI) section of the AM437x ARM Cortex-A9
Microprocessors (MPUs) Technical Reference Manual (SPRUHL7).
5.12.13.1 McSPI Electrical Data and Timing
The following timings are applicable to the different configurations of McSPI in master or slave mode for any
McSPI and any channel (n).
5.12.13.1.1 McSPI—Slave Mode
Table 5-89. McSPI Timing Conditions—Slave Mode
TIMING CONDITION PARAMETER
MIN
MAX
UNIT
Input Conditions
tr
Input signal rise time
5
ns
tf
Input signal fall time
5
ns
Output Condition
Cload
Output load capacitance
20
pF
Table 5-90. Timing Requirements for McSPI Input Timings—Slave Mode
(see Figure 5-106)
OPP100
OPP50
NO.
UNIT
MIN
MAX
MIN
MAX
1
tc(SPICLK)
Cycle time, SPI_CLK
62.5
83.2
ns
2
tw(SPICLKL)
Typical Pulse duration, SPI_CLK low
0.45P(1)
0.45P(1)
0.45P(1)
0.45P(1)
ns
3
tw(SPICLKH)
Typical Pulse duration, SPI_CLK high
0.45P(1)
0.45P(1)
0.45P(1)
0.45P(1)
ns
Setup time, SPI_D[x] (SIMO) valid before SPI_CLK
4
tsu(SIMO-SPICLK)
12
13
ns
active edge(2)(3)
Hold time, SPI_D[x] (SIMO) valid after SPI_CLK
5
th(SPICLK-SIMO)
12
13
ns
active edge(2)(3)
Setup time, SPI_CS valid before SPI_CLK first
8
tsu(CS-SPICLK)
12
13
ns
edge(2)
9
th(SPICLK-CS)
Hold time, SPI_CS valid after SPI_CLK last edge(2)
12
13
ns
(1) P = SPI_CLK period.
(2) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(3) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
Table 5-91. Switching Characteristics for McSPI Output Timings—Slave Mode
(see Figure 5-107)
OPP100
OPP50
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Delay time, SPI_CLK active edge to
6
td(SPICLK-SOMI)
17
0
19
ns
SPI_D[x] (SOMI) transition(1)(2)
Delay time, SPI_CS active edge to SPI_D[x]
7
td(CS-SOMI)
26
29
ns
(SOMI) transition(2)
(1) This timing applies to all configurations regardless of MCSPIX_CLK polarity and which clock edges are used to drive output data and
capture input data.
(2) Pins SPIx_D0 and SPIx_D1 can function as SIMO or SOMI.
224
Specifications
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