AM4376 datasheet(222/261 Pages) TI

222 / 261 page

AM4376, AM4377, AM4378, AM4379

SPRS851B – JUNE 2014 – REVISED APRIL 2015

www.ti.com

Table 5-88. Switching Characteristics for McASP(1)

(see Figure 5-105)

OPP100

OPP50

NO.

UNIT

MIN

MAX

MIN

MAX

Cycle time, McASP[x]_AHCLKR and

tc(AHCLKRX)

20(2)

38.46

McASP[x]_AHCLKX

Pulse duration, McASP[x]_AHCLKR and

tw(AHCLKRX)

0.5P - 2.5(3)

McASP[x]_AHCLKX high or low

Cycle time, McASP[x]_ACLKR and

tc(ACLKRX)

38.46

McASP[x]_ACLKX

Pulse duration, McASP[x]_ACLKR and

tw(ACLKRX)

0.5P - 2.5(3)

McASP[x]_ACLKX high or low

ACLKR and

Delay time, McASP[x]_ACLKR and

7.25

8.5

ACLKX int

McASP[x]_ACLKX transmit edge to

McASP[x]_AFSR and

ACLKR and

2.7

McASP[x]_AFSX output valid

ACLKX ext in

td(ACLKRX-AFSRX)

Delay time, McASP[x]_ACLKR and

McASP[x]_ACLKX transmit edge to

ACLKR and

McASP[x]_AFSR and

ACLKX ext

2.7

McASP[x]_AFSX output valid with

out

Pad Loopback

Delay time, McASP[x]_ACLKX

ACLKX int

7.25

8.5

transmit edge to McASP[x]_AXR

ACLKX ext in

2.7

output valid

td(ACLKX-AXR)

Delay time, McASP[x]_ACLKX

ACLKX ext

transmit edge to McASP[x]_AXR

2.7

out

output valid with Pad Loopback

Disable time, McASP[x]_ACLKX

ACLKX int

7.25

8.5

transmit edge to McASP[x]_AXR

ACLKX ext in

2.7

output high impedance

tdis(ACLKX-AXR)

Disable time, McASP[x]_ACLKX

transmit edge to McASP[x]_AXR

ACLKX ext

2.7

output high impedance with Pad

out

Loopback

(1) ACLKR internal: ACLKRCTL.CLKRM = 1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0

ACLKR external output: ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1

ACLKX internal: ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0

ACLKX external output: ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1

(2) 50 MHz

(3) P = AHCLKR and AHCLKX period.

222

Specifications

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