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AM5728 Datasheet(PDF) 18 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 415 page  AM5728, AM5726 SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 www.ti.com Table 4-2. Ball Characteristics (continued) BALL BALL BALL RESET I/O PULL MUXMODE RESET POWER BUFFER BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 28/26 [4] TYPE [6] RESET REL. VOLTAGE HYS [12] UP/DOWN DSIS [15] [5] REL. [11] TYPE [13] STATE [7] MUXMODE VALUE [10] TYPE [14] STATE [8] [9] N20 ddr2_a7 ddr2_a7 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR P27 ddr2_a8 ddr2_a8 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR N27 ddr2_a9 ddr2_a9 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR U23 ddr2_ba0 ddr2_ba0 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR U27 ddr2_ba1 ddr2_ba1 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR U26 ddr2_ba2 ddr2_ba2 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR U28 ddr2_casn ddr2_casn 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR T28 ddr2_ck ddr2_ck 0 O PD drive clk 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR U24 ddr2_cke ddr2_cke 0 O PD drive 0 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR P24 ddr2_csn0 ddr2_csn0 0 O PD drive 1 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy (OFF) DDR E26 ddr2_d0 ddr2_d0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR G25 ddr2_d1 ddr2_d1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR H24 ddr2_d10 ddr2_d10 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR H26 ddr2_d11 ddr2_d11 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR G26 ddr2_d12 ddr2_d12 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR J25 ddr2_d13 ddr2_d13 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR J26 ddr2_d14 ddr2_d14 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR J24 ddr2_d15 ddr2_d15 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L22 ddr2_d16 ddr2_d16 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR K20 ddr2_d17 ddr2_d17 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR K21 ddr2_d18 ddr2_d18 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L23 ddr2_d19 ddr2_d19 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR F25 ddr2_d2 ddr2_d2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR 18 Terminal Configuration and Functions Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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