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AM5728 Datasheet(PDF) 19 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 415 page  AM5728, AM5726 www.ti.com SPRS915O – MARCH 2014 – REVISED OCTOBER 2015 Table 4-2. Ball Characteristics (continued) BALL BALL BALL RESET I/O PULL MUXMODE RESET POWER BUFFER BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] 28/26 [4] TYPE [6] RESET REL. VOLTAGE HYS [12] UP/DOWN DSIS [15] [5] REL. [11] TYPE [13] STATE [7] MUXMODE VALUE [10] TYPE [14] STATE [8] [9] L24 ddr2_d20 ddr2_d20 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR J23 ddr2_d21 ddr2_d21 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR K22 ddr2_d22 ddr2_d22 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR J20 ddr2_d23 ddr2_d23 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L27 ddr2_d24 ddr2_d24 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L26 ddr2_d25 ddr2_d25 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L25 ddr2_d26 ddr2_d26 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR L28 ddr2_d27 ddr2_d27 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR M23 ddr2_d28 ddr2_d28 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR M24 ddr2_d29 ddr2_d29 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR F24 ddr2_d3 ddr2_d3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR M25 ddr2_d30 ddr2_d30 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR M26 ddr2_d31 ddr2_d31 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR F26 ddr2_d4 ddr2_d4 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR F27 ddr2_d5 ddr2_d5 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR E27 ddr2_d6 ddr2_d6 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR E28 ddr2_d7 ddr2_d7 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR H23 ddr2_d8 ddr2_d8 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR H25 ddr2_d9 ddr2_d9 0 IO PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR F28 ddr2_dqm0 ddr2_dqm0 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR G24 ddr2_dqm1 ddr2_dqm1 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR K23 ddr2_dqm2 ddr2_dqm2 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR M22 ddr2_dqm3 ddr2_dqm3 0 O PU PU 1.35/1.5/1.8 vdds_ddr2 No LVCMOS Pux/PDy DDR Copyright © 2014–2015, Texas Instruments Incorporated Terminal Configuration and Functions 19 Submit Documentation Feedback Product Folder Links: AM5728 AM5726 |
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