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DM385 Datasheet(PDF) 165 Page - Texas Instruments

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Part # DM385
Description  DM385 and DM388 DaVinci??Digital Media Processor
PDF  281 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM385 Datasheet(HTML) 165 Page - Texas Instruments

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DM385, DM388
www.ti.com
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
8.4
EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.
8.4.1
EDMA Channel Synchronization Events
The EDMA channel controller supports up to 64 channels which service peripherals and memory. Each
EDMA channel is mapped to a default EDMA synchronization event as shown in Table 8-2. In addition,
each EDMA channel can alternatively be mapped to one of the 31 multiplexed EDMA synchronization
events shown in Table 8-3. The EVT_MUX_x registers in the Control Module are used to select between
the default event and the multiplexed events for each channel.
For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, cleared, and more, see the Enhanced Direct Memory Access Controller
chapter in the device-specific Technical Reference Manual.
Table 8-2. EDMA Default Synchronization Events
EVENT
DEFAULT
DEFAULT EVENT DESCRIPTION
NUMBER
EVENT NAME
0-1
–
Reserved
2
SDTXEVT1
SD1 Transmit
3
SDRXEVT1
SD1 Receive
4-7
–
Reserved
8
AXEVT0
McASP0 Transmit
9
AREVT0
McASP0 Receive
10
AXEVT1
McASP1 Transmit
11
AREVT1
McASP1 Receive
12
–
Reserved
13
–
Reserved
14
–
Reserved
15
–
Reserved
16
SPI0XEVT0
SPI0 Transmit 0
17
SPI0REVT0
SPI0 Receive 0
18
SPI0XEVT1
SPI0 Transmit 1
19
SPI0REVT1
SPI0 Receive 1
20
SPI0XEVT2
SPI0 Transmit 2
21
SPI0REVT2
SPI0 Receive 2
22
SPI0XEVT3
SPI0 Transmit 3
23
SPI0REVT3
SPI0 Receive 3
24
SDTXEVT0
SD0 Transmit
25
SDRXEVT0
SD0 Receive
26
UTXEVT0
UART0 Transmit
27
URXEVT0
UART0 Receive
28
UTXEVT1
UART1 Transmit
29
URXEVT1
UART1 Receive
30
UTXEVT2
UART2 Transmit
31
URXEVT2
UART2 Receive
32-35
–
Reserved
36
ISS_DMA_REQ1
ISS Event 1
37
ISS_DMA_REQ2
ISS Event 2
38
ISS_DMA_REQ3
ISS Event 3
Copyright © 2013, Texas Instruments Incorporated
Peripheral Information and Timings
165
Submit Documentation Feedback
Product Folder Links: DM385 DM388



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