DM385 datasheet(201/281 Pages) TI

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DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

8.10 High-Definition Video Processing Subsystem (HDVPSS)

The device High-Definition Video Processing Subsystem (HDVPSS) provides a video input interface for

external imaging peripherals (for example, image sensors, video decoders, and more) and a video output

interface for display devices, such as analog SDTV and HDTV displays, digital HDTV displays, digital LCD

panels, and more. It includes HD and SD video encoders and an HDMI transmitter interface.

The device HDVPSS features include:

•

Two display processing pipelines with de-interlacing, scaling, alpha blending, chroma keying, color

space conversion, flicker filtering, and pixel format conversion.

•

HD/SD compositor features for PIP support.

•

Format conversions (up to 1080p 60 Hz) include scan format conversion, scan rate conversion, aspect-

ratio conversion, and frame size conversion.

•

Supports additional video processing capabilities by using the subsystem's memory-to-memory feature.

•

Two parallel video processing pipelines support HD (up to 1080p60) and SD (NTSC/PAL)

simultaneous outputs.

–

HD analog component output with OSD and embedded timing codes (BT.1120)

•

3-channel HD-DAC with 10-bit resolution.

•

External HSYNC and VSYNC signals.

–

SD analog output with OSD with embedded timing codes (BT.656)

•

Composite output

•

1-channel SD-DAC with 10-bit resolution

•

Options available to support MacroVision and CGMS-A (contact local TI Sales rep for

information).

–

Digital HDMI 1.3a-compliant transmitter (for details, see Section 8.9, High-Definition Multimedia

Interface (HDMI)).

–

One digital video output supporting up to 30-bits @ 165 MHz

–

One digital video output supporting up to 24-bits @ 165 MHz

–

Supports clock inversion for VOUT[0] and VOUT[1] clock signals.

•

Two independently configurable external video input capture ports (up to 165 MHz).

–

16/24-bit HD digital video input or dual clock independent 8-bit SD inputs on each capture port.

–

8/16/24-bit digital video input

–

8-bit digital video input

–

Embedded sync and external sync modes are supported for all input configurations (VIN1 Port B

supports embedded sync only).

–

De-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams, effectively supporting up

to 16 simultaneous SD inputs with a glueless interface to an external multiplexer such as the

TVP5158.

–

Additional

features

include:

programmable

color

space

conversion,

scaler

and

chroma

downsampler, ancillary VANC/VBI data capture (decoded by software).

•

Graphics features:

–

Three independently-generated graphics layers.

–

Each supports full-screen resolution graphics in HD, SD or both.

–

Up/down scaler optimized for graphics.

–

Global and pixel-level alpha blending supported.

For more detailed information on specific features and registers, see the High Definition Video Processing

Subsystem chapter in the device-specific Technical Reference Manual.

Peripheral Information and Timings

201

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