DM385 datasheet(202/281 Pages) TI

202 / 281 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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8.10.1 HDVPSS Electrical Data/Timing

Table 8-35. Timing Requirements for HDVPSS Input

(see Figure 8-38 and Figure 8-39)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

VIN[X]A_CLK

tc(CLK)

Cycle time, VIN[x]A_CLK

6.06(1)

tw(CLKH)

Pulse duration, VIN[x]A_CLK high (45% of tc)

2.73

tw(CLKH)

Pulse duration, VIN[x]A_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VIN[x]A_CLK (10%-90%)

2.64

tsu(DE-CLK)

tsu(VSYNC-CLK)

Input setup time, control valid to VIN[x]A_CLK high/low

3.11

tsu(FLD-CLK)

tsu(HSYNC-CLK)

tsu(D-CLK)

Input setup time, data valid to VIN[x]A_CLK high/low

3.11

th(CLK-DE)

th(CLK-VSYNC)

Input hold time, control valid from VIN[x]A_CLK high/low

-0.5

th(CLK-FLD)

th(CLK-HSYNC)

th(CLK-D)

Input hold time, data valid from VIN[x]A_CLK high/low

-0.5

VIN[x]B_CLK

tc(CLK)

Cycle time, VIN[x]B_CLK

6.06(1)

tw(CLKH)

Pulse duration, VIN[x]B_CLK high (45% of tc)

2.73

tw(CLKH)

Pulse duration, VIN[x]B_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VIN[x]B_CLK (10%-90%)

2.64

tsu(DE-CLK)

tsu(VSYNC-CLK)

Input setup time, control valid to VIN[x]B_CLK high/low

3.11

tsu(FLD-CLK)

tsu(HSYNC-CLK)

tsu(D-CLK)

Input setup time, data valid to VIN[x]B_CLK high/low

3.11

th(CLK-DE)

th(CLK-VSYNC)

Input hold time, control valid from VIN[x]B_CLK high/low

-0.5

th(CLK-FLD)

th(CLK-HSYNC)

th(CLK-D)

Input hold time, data valid from VIN[x]B_CLK high/low

-0.5

(1)

For maximum frequency of 165 MHz.

202

Peripheral Information and Timings

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