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DM385 Datasheet(PDF) 206 Page - Texas Instruments

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Part # DM385
Description  DM385 and DM388 DaVinci??Digital Media Processor
PDF  281 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM385 Datasheet(HTML) 206 Page - Texas Instruments

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DM385, DM388
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
www.ti.com
Table 8-37. Static and Dynamic SD-DAC Specifications
VDAC STATIC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference Current Setting Resistor
Normal Mode
4653
4700
4747
Ω
(RSET)
TVOUT Bypass Mode
9900
10000
10100
Ω
Output resistor between TV_OUT0
Normal Mode
2673
2700
2727
Ω
and TV_VFB0 pins (ROUT)
TVOUT Bypass Mode
N/A
Load Resistor (RLOAD)
Normal Mode
75-
Ω Inside the Display
TVOUT Bypass Mode
1485
1500
1515
Ω
AC-Coupling Capacitor (Optional)
Normal Mode
220
uF
[CAC]
TVOUT Bypass Mode
See External Amplifier Specification
Total Capacitance from TV_OUT0
Normal Mode
300
pF
to VSSA_VDAC_1P8
TVOUT Bypass Mode
N/A
Resolution
10
Bits
Integral Non-Linearity (INL), Best
Normal Mode
-4
4
LSB
Fit
TVOUT Bypass Mode
-1
1
LSB
Differential Non-Linearity (DNL)
Normal Mode
-2.5
2.5
LSB
TVOUT Bypass Mode
-1
1
LSB
Full-Scale Output Voltage
Normal Mode (RLOAD = 75 Ω)
1.3
V
TVOUT Bypass Mode (RLOAD =
0.7
V
1.5 k
Ω)
Full-Scale Output Current
Normal Mode
N/A
TVOUT Bypass Mode
470
uA
Gain Error
Normal Mode (Composite) and
-10
10
%FS
TVOUT Bypass Mode
Output Impedance
Looking into TV_OUT0 nodes
75
Ω
VDAC DYNAMIC SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output Update Rate (FCLK)
54
60
MHz
Signal Bandwidth
3 dB
6
MHz
Spurious-Free Dynamic Range
FCLK = 54 MHz, FOUT = 1 MHz
50
dBc
(SFDR) within bandwidth
Signal-to-Noise Ration (SNR)
FCLK = 54 MHz, FOUT = 1 MHz
54
dB
Normal Mode, 100 mVpp @ 6
6
MHz on VDDA_VDAC_1P8
Power Supply Rejection (PSR)
dB
TVOUT Bypass Mode, 100
mVpp @ 6 MHz on
20
VDDA_VDAC_1P8
206
Peripheral Information and Timings
Copyright © 2013, Texas Instruments Incorporated
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Product Folder Links: DM385 DM388



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