DM385 datasheet(208/281 Pages) TI

208 / 281 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

www.ti.com

•

To provide adequate ESD protection on the VGA/YPbPr output, recommend the following:

–

Provide ESD protection on all output signals (that is, Video, Syncs and DDC I/F).

–

Minimize the distance from the ESD protection device to the VGA/YPbPr output connector.

–

Mount all ESD protection devices on the PCB level next to the ground plane to provide the lowest

possible impedance path to ground.

–

Provide a low impedance path to ground for the shield of the VGA/YPbPr output connector.

•

For VGA outputs, recommend the following:

–

3.3 V to 5 V level shifters should be used for the H/V Sync signals.

–

3.3 V to 5 V bi-directional level shifters should be used for the DDC signals. This is typically

implemented using two N-channel enhancement MOSFETs.

–

Recommend using the TPD7S019 ESD protection device with integrated level shifters for the H/V

Sync and DDC signals.

–

The source impedance of the H/V Sync outputs should be 50

Ω.

–

The characteristic impedance of the H/V Sync output signal traces should be 50

Ω.

–

The THS7360 reconstruction filter should be bypassed to provide maximum bandwidth.

–

The 5-V supply output should be current limited (for example, using a series resistor or resettable

fuse).

For additional video HD-DAC design guidelines, see the High Definition Video Processing Subsystem

chapter in the device-specific Technical Reference Manual.

Table 8-38. HD-DAC Recommended Operating Conditions

MIN

NOM

MAX

UNIT

Output Load Capacitance (CLOAD)

(1)

Output Load Resistors (RLOAD)

–1%

165

+1%

Full-Scale Current Adjust Resistor (RHDDAC_IREF)

–1%

2.67

+1%

Optional External Voltage Reference (HDDAC_VREF)(2)

–5%

467

+5%

Required External Amplification (THS7360)

–3%

4.5

+3%

V/V

(1)

The output load capacitance includes the signal trace parasitic capacitance and the video buffer input capacitance.

(2)

An external voltage reference is not required since an internal bandgap reference is provided.

Table 8-39. HD-DAC Specifications

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Bits

DC Accuracy

Integral Non-Linearity (INL), best fit

2.5

LSB

Differential Non-Linearity (DNL)

1.0

LSB

Analog Output

Full-Scale Output Current (IFS)

DAC input = 1023

Full-Scale Output Voltage (VFS)

DAC input = 1023

–15%

494

+15%

Zero Scale Offset Error (ZSET)

0.5

LSB

Channel matching

Dynamic Specifications

Maximum Output Update Rate (FCLK)

150

MHz

Spurious - Free Dynamic Range (SFDR)

FCLK = 74.25 MHz,

30-MHz full-scale sine wave

FCLK = 148.5 MHz,

30-MHz full-scale sine wave

208

Peripheral Information and Timings

Submit Documentation Feedback

Product Folder Links: DM385 DM388

DM385 Datasheet(PDF) 208 Page - Texas Instruments

DM385 Datasheet(HTML) 208 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL