DM385 datasheet(203/281 Pages) TI

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VIN[x]A_CLK/

VIN[x]B_CLK/

VOUT[x]_CLK

DM385, DM388

www.ti.com

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

Table 8-36. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output

(see Figure 8-38 and Figure 8-40)

OPP100/OPP120/Turbo/

Nitro

NO.

PARAMETER

UNIT

MIN

MAX

tc(CLK)

Cycle time, VOUT[x]_CLK

6.06(1)

tw(CLKH)

Pulse duration, VOUT[x]_CLK high (45% of tc)

2.73

tw(CLKL)

Pulse duration, VOUT[x]_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VOUT[x]_CLK (10%-90%)

2.64

td(CLK-AVID)

td(CLK-FLD)

Delay time, VOUT[x]_CLK low (falling) to control valid, positive

1.64

4.18

clock edge

td(CLK-VSYNC)

td(CLK-HSYNC)

td(CLK-RCR)

Delay time, VOUT[0]_CLK low (falling) to data valid, positive clock

td(CLK-GYYC)

edge

td(CLK-BCBC)

1.64

4.18

td(CLK-YYC)

Delay time, VOUT[1]_CLK low (falling) to data valid, positive clock

edge

td(CLK-C)

td(CLK-AVID)

td(CLK-FLD)

Delay time, VOUT[x]_CLK low (falling) to control valid, negative

-1.64

4.18

clock edge

td(CLK-VSYNC)

td(CLK-HSYNC)

td(CLK-RCR)

Delay time, VOUT[0]_CLK low (falling) to data valid, negative clock

td(CLK-GYYC)

edge

td(CLK-BCBC)

-1.64

4.18

td(CLK-YYC)

Delay time, VOUT[1]_CLK low (falling) to data valid, negative clock

edge

td(CLK-C)

(1)

For maximum frequency of 165 MHz.

Figure 8-38. HDVPSS Clock Timing

Peripheral Information and Timings

203

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