DM385 datasheet(252/281 Pages) TI

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DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

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8.14.3 McASP (McASP[1:0]) Electrical Data/Timing

Table 8-72. Timing Requirements for McASP(1)

(see Figure 8-83)

OPP100/OPP120/

Turbo/Nitro

NO.

UNIT

MIN

MAX

tc(AHCLKRX)

Cycle time, MCA[x]_AHCLKR/X

0.5P -

tw(AHCLKRX)

Pulse duration, MCA[x]_AHCLKR/X high or low

2.5(2)

tc(ACLKRX)

Cycle time, MCA[x]_ACLKR/X

0.5R -

tw(ACLKRX)

Pulse duration, MCA[x]_ACLKR/X high or low

2.5(3)

ACLKR/X int

10.5

Setup time, MCA[x]_AFSR/X input valid before

tsu(AFSRX-ACLKRX)

ACLKR/X ext in

MCA[X]_ACLKR/X

ACLKR/X ext out

ACLKR/X int

-1

Hold time, MCA[x]_AFSR/X input valid after

th(ACLKRX-AFSRX)

ACLKR/X ext in

MCA[X]_ACLKR/X

ACLKR/X ext out

ACLKR/X int

10.5

Setup time, MCA[x]_AXR input valid before

tsu(AXR-ACLKRX)

ACLKR/X ext in

MCA[X]_ACLKR/X

ACLKR/X ext out

ACLKR/X int

-1

Hold time, MCA[x]_AXR input valid after

th(ACLKRX-AXR)

ACLKR/X ext in

MCA[X]_ACLKR/X

ACLKR/X ext out

(1)

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2)

P = MCA[x]_AHCLKR/X period in nano seconds (ns).

(3)

R = MCA[x]_ACLKR/X period in ns.

252

Peripheral Information and Timings

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