DM385 datasheet(257/281 Pages) TI

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Start

End

SDx_CLK

SDx_DAT[x]

START

END

SDx_CLK

SDx_DAT[x]

START

XMIT

Valid

END

SDx_CLK

SDx_CMD

START

XMIT

Valid

END

SDx_CLK

SDx_CMD

DM385, DM388

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SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

Table 8-75. Switching Characteristics Over Recommended Operating Conditions for

MMC/SD/SDIO (continued)

(see Figure 8-85 through Figure 8-88)

OPP100/OPP120/

Turbo/Nitro

MODES

NO.

PARAMETER

UNIT

3.3 V STD

3.3 V HS

1.8 V SDR12

1.8 V SDR25

MIN

MAX

MIN

MAX

tr(CLK)

Rise time, All Signals (10% to 90%)

2.2

tf(CLK)

Fall time, All Signals (10% to 90%)

2.2

Delay time, SD_CLK rising clock edge to SD_CMD

td(CLKL-CMD)

-4

2.3

transition

Delay time, SD_CLK rising clock edge to SD_DATx

td(CLKL-DAT)

-4

2.3

transition

Figure 8-85. MMC/SD/SDIO Host Command Timing

Figure 8-86. MMC/SD/SDIO Card Response Timing

Figure 8-87. MMC/SD/SDIO Host Write Timing

Figure 8-88. MMC/SD/SDIO Host Read and Card CRC Status Timing

Peripheral Information and Timings

257

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