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DM385 Datasheet(PDF) 262 Page - Texas Instruments |
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DM385 Datasheet(HTML) 262 Page - Texas Instruments |
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262 / 281 page  DM385, DM388 SPRS821D – MARCH 2013 – REVISED DECEMBER 2013 www.ti.com 8.17.2 SPI Electrical Data/Timing Table 8-79. Timing Requirements for SPI - Master Mode (see Figure 8-89 and Figure 8-90) OPP100/OPP120/ Turbo/Nitro NO. UNIT MIN MAX MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0)1 LOAD AT A MAXIMUM OF 5 pF 1 tc(SPICLK) Cycle time, SPI_CLK(1)(2) 20.8(3) ns 2 tw(SPICLKL) Pulse duration, SPI_CLK low(1) 0.5*P - 1(4) ns 3 tw(SPICLKH) Pulse duration, SPI_CLK high(1) 0.5*P - 1(4) ns SPI0, SPI1 2.29 Setup time, SPI_D[x] valid before SPI_CLK active 4 tsu(MISO-SPICLK) ns edge(1) SPI2, SPI3 4 5 th(SPICLK-MISO) Hold time, SPI_D[x] valid after SPI_CLK active edge (1) 2.67 ns 6 td(SPICLK-MOSI) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) 3.57 ns 7 td(SCS-MOSI) Delay time, SPI_SCS[x] active edge to SPI_D[x] transition 3.57 ns MASTER_PH B-4.2(6) ns A0(5) Delay time, SPI_SCS[x] active to SPI_CLK first 8 td(SCS-SPICLK) edge(1) MASTER_PH A-4.2(7) ns A1(5) MASTER_PH A-4.2(7) ns A0(5) Delay time, SPI_CLK last edge to SPI_SCS[x] 9 td(SPICLK-SCS) inactive(1) MASTER_PH B-4.2(6) ns A1(5) MASTER: SPI0, SPI1, SPI2 (M0) and SPI3 (M0) LOAD AT MAX 25pF MASTER: SPI2 (M1, M2, M3) and SPI3 (M1, M2, M3) 1 to 4 LOAD AT 5 to 25pF 1 tc(SPICLK) Cycle time, SPI_CLK(1)(2) 41.7(8) ns 2 tw(SPICLKL) Pulse duration, SPI_CLK low(1) 0.5*P - 2(4) ns 3 tw(SPICLKH) Pulse duration, SPI_CLK high(1) 0.5*P - 2(4) ns SPI0, SPI1 4 Setup time, SPI_D[x] valid before SPI_CLK active 4 tsu(MISO-SPICLK) ns edge(1) SPI2, SPI3 6 5 th(SPICLK-MISO) Hold time, SPI_D[x] valid after SPI_CLK active edge (1) 3.8 ns 6 td(SPICLK-MOSI) Delay time, SPI_CLK active edge to SPI_D[x] transition (1) -5.5 5.5 ns 7 td(SCS-MOSI) Delay time, SPI_SCS[x] active edge to SPI_D[x] transition 5.5 ns MASTER_PH B-3.5(6) ns A0(5) Delay time, SPI_SCS[x] active to SPI_CLK first 8 td(SCS-SPICLK) edge(1) MASTER_PH A-3.5(7) ns A1(5) MASTER_PH A-3.5(7) ns A0(5) Delay time, SPI_CLK last edge to SPI_SCS[x] 9 td(SPICLK-SCS) inactive(1) MASTER_PH B-3.5(6) ns A1(5) (1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data. (2) Related to the SPI_CLK maximum frequency. (3) Maximum frequency = 48 MHz (4) P = SPICLK period. (5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register. (6) B = (TCS + 0.5) * TSPICLKREF * Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2. (7) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. (8) Maximum frequency = 24 MHz 262 Peripheral Information and Timings Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DM385 DM388 |
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