W989D6KB datasheet(4/66 Pages) WINBOND

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W989D6KB / W989D2KB

512Mb Mobile LPSDR

Publication Release Date : October 07, 2013

- 4 -

Revision : A01-003

9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) .......................... 26

9.4 Burst Termination........................................................................................................................... 26

9.5 Mode Register Operation ............................................................................................................... 27

9.5.1 Burst Length field (A2~A0) ....................................................................................................................... 27

9.5.2 Addressing Mode Select (A3) .................................................................................................................. 27

9.5.3 Addressing Sequence for Sequential Mode............................................................................................. 28

9.5.4 Addressing Sequence for Interleave Mode .............................................................................................. 28

9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13).......................................... 29

9.5.6 Read Cycle CAS Latency = 3................................................................................................................ 29

9.5.7 CAS Latency field (A6~A4).................................................................................................................... 30

9.5.8 Mode Register Definition .......................................................................................................................... 30

9.6 Extended Mode Register Description ............................................................................................. 31

9.7 Simplified State Diagram................................................................................................................ 32

10. CONTROL TIMING WAVEFORMS ......................................................................................... 33

10.1 Command Input Timing ................................................................................................................ 33

10.2 Read Timing................................................................................................................................. 34

10.3 Control Timing of Input Data (x16) ............................................................................................... 35

10.4 Control Timing of Output Data (x16)............................................................................................. 36

10.5 Control Timing of Input Data (x32) ............................................................................................... 37

10.6 Control Timing of Output Data (x32)............................................................................................. 38

10.7 Mode register Set (MRS) Cycle .................................................................................................... 39

10.8 Extended Mode register Set (EMRS) Cycle.................................................................................. 40

11. OPERATING TIMING EXAMPLE ............................................................................................ 41

11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ..................................................... 41

11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)........................... 42

11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ..................................................... 43

11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)........................... 44

11.5 Interleaved Bank Write (Burst Length = 8).................................................................................... 45

11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge) ......................................................... 46

11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ............................................................. 47

11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) .................................................. 48

11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ....................................................... 49

11.10 Auto Precharge Write (Burst Length = 4).................................................................................... 50

11.11 Auto Refresh Cycle .................................................................................................................... 51

11.12 Self Refresh Cycle ..................................................................................................................... 52

11.13 Power Down Mode ..................................................................................................................... 53

11.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) .......................................... 54

11.15 Deep Power Down Mode Entry .................................................................................................. 55

11.16 Deep Power Down Mode Exit..................................................................................................... 56

11.17 Auto Precharge Timing (Read Cycle) ......................................................................................... 57

11.19 Timing Chart of Read to Write Cycle .......................................................................................... 59

11.20 Timing Chart for Write to Read Cycle ......................................................................................... 59

11.21 Timing Chart for Burst Stop Cycle (Burst Stop Command) ......................................................... 60

11.22 Timing Chart for Burst Stop Cycle (Precharge Command) ......................................................... 60

11.23 CKE/DQM Input Timing (Write Cycle) ........................................................................................ 61

11.24 CKE/DQM Input Timing (Read Cycle) ........................................................................................ 62

12. PACKAGE DIMENSION.......................................................................................................... 63

12.1 : LPSDR X 16............................................................................................................................... 63

12.2 : LPSDR X 32............................................................................................................................... 64

13.REVISION HISTORY ................................................................................................................ 65

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