TLE9263QX datasheet(114/164 Pages) INFINEON

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Data Sheet

114

Rev. 1.1, 2014-09-26

TLE9263QX

Serial Peripheral Interface

16.1

SPI Block Description

The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK

provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 55).

The transmission cycle begins when the chip is selected by the input CSN (Chip Select Not), LOW active. After

the CSN input returns from LOW to HIGH, the word that has been read is interpreted according to the content.

The SDO output switches to tristate status (high impedance) at this point, thereby releasing the SDO bus for other

use.The state of SDI is shifted into the input register with every falling edge on CLK. The state of SDO is shifted

out of the output register after every rising edge on CLK. The SPI of the SBC is not daisy chain capable.

Figure 55

SPI Data Transfer Timing (note the reversed order of LSB and MSB shown in this figure

compared to the register description)

1 2 3 4 5 6 7 8 9 10

0 1 2 3 4 5 6

11 12 13 14

7 8 9 10

CSN high to low: SDO is enabled. Status information transferred to output shift register

CSN low to high: data from shift register is transferred to output functions

SDI: will accept data on the falling edge of CLK signal

SDO: will change state on the rising edge of CLK signal

Actual status

11 12 13 14

Actual data

New data

New status

SDO

SDI

CSN

CLK

time

ERR

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