PGND

PGND

PGND

PGND

AGND

LX2

LX2

LX1

LX1

V7V

G

G

PGND

PGND

2

1

PGND

PGND

V7V

VIN2

VIN1

PGND

VOUT2

VOUT1

PGND

PGND

EN1

EN2

SDA

SCL

DVCC

LX1

LX1

LX2

LX2

PGND

AGND

TPS65276

www.ti.com

SLVSC83A – AUGUST 2013 – REVISED DECEMBER 2013

PCB Layout Guideline

TPS65276 can be layout on 2-layer PCB illustrated below.

Layout is a critical portion of good power supply design. See Figure 38 for a PCB layout example. The top layer

contains the main power traces for VIN, VOUT, and VLX. Also on the top layer are connections for the remaining

pins of the TPS65276 and a large top side area filled with ground. The top layer ground area should be

connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and

directly under the TPS65276 device to provide a thermal path from the exposed thermal pad land to ground. The

bottom layer acts as ground plane connecting analog ground and power ground.

The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated

load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating

area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor

with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor

connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a

low ESR ceramic capacitor with X5R or X7R dielectric.

Since the LX connection is the switching node, the output inductor should be located close to the LX pins, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor

ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this

conductor length while maintaining adequate width. The additional external components can be placed

approximately as shown.

Figure 38. TPS65276 Layout on 2-layer PCB

Copyright © 2013, Texas Instruments Incorporated

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Product Folder Links: TPS65276