KAI-2001 datasheet(8/36 Pages) ONSEMI

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KAI−2001

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Output

Figure 7. Output Architecture

VDD

VOUT

Floating

Diffusion

HCCD

Charge

Transfer

Source

Follower

Source

Follower

Source

Follower

H2B

H1S

H1B

H2S

H2B

H1S

VDD

VSS

Charge packets contained in the horizontal register are

dumped pixel by pixel onto the floating diffusion (FD)

output node whose potential varies linearly with the quantity

of charge in each packet. The amount of potential charge is

determined

the

expression

DVFD = DQ/CFD.

A three-stage source-follower amplifier is used to buffer

this signal voltage off chip with slightly less than unity gain.

The translation from the charge domain to the voltage

domain is quantified by the output sensitivity or charge to

voltage conversion in terms of microvolts per electron

(

mV/e−). After the signal has been sampled off chip, the reset

clock (R) removes the charge from the floating diffusion and

resets its potential to the reset drain voltage (RD).

When the image sensor is operated in the binned or

summed interlaced modes there will be more than 40,000 e−

in the output signal. The image sensor is designed with

a16

mV/e charge to voltage conversion on the output. This

means a full signal of 40,000 electrons will produce

a 640 mV change on the output amplifier. The output

amplifier was designed to handle an output swing of 640 mV

at a pixel rate of 40 MHz. If 80,000 electron charge packets

are generated in the binned or summed interlaced modes

then the output amplifier output will have to swing

1,280 mV. The output amplifier does not have enough

bandwidth (slew rate) to handle 1,280 mV at 40 MHz.

Hence, the pixel rate will have to be reduced to 20 MHz if

the full dynamic range of 80,000 electrons is desired.

The charge handling capacity of the output amplifier is

also set by the reset clock voltage levels. The reset clock

driver circuit is very simple if an amplitude of 5 V is used.

But the 5 V amplitude restricts the output amplifier charge

capacity to 40,000 electrons. If the full dynamic range of

80,000 electrons is desired then the reset clock amplitude

will have to be increased to 7 V.

If you only want a maximum signal of 40,000 electrons in

binned or summed interlaced modes, then a 40 MHz pixel

rate with a 5 V reset clock may be used. The output of the

amplifier will be unpredictable above 40,000 electrons so be

sure to set the maximum input signal level of your analog to

digital converter to the equivalent of 40,000 electrons

(640 mV).

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