KAI−2001

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21

AC Operating Conditions

Table 11. CLOCK LEVELS

Description

Symbol

Min.

Nom.

Max.

Unit

Notes

Vertical CCD Clock High

V2H

7.5

8.0

8.5

V

Vertical CCD Clocks Midlevel

V1M, V2M

−0.2

0.0

0.2

V

Vertical CCD Clocks Low

V1L, V2L

−9.5

−9.0

−8.5

V

Horizontal CCD Clocks Amplitude

H1H, H2H

4.5

5.0

5.5

V

Horizontal CCD Clocks Low

H1L, H2L

−5.0

−4.0

−3.8

V

Reset Clock Amplitude

RH

−

5.0

−

V

1

Reset Clock Low

RL

−4.0

−3.5

−3.0

V

2

Electronic Shutter Voltage

44

48

52

V

3

Fast Dump High

FDH

4.8

5.0

5.2

V

Fast Dump Low

FDL

−9.5

−9.0

−8.0

V

1. Reset amplitude must be set to 7.0 V for 80,000 electrons output in summed interlaced or binning modes.

2. Reset low level must be set to –5.0 V for 80,000 electrons output in summed interlaced or binning modes.

3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions.

Clock Line Capacitances

Figure 18. Clock Line Capacitances

V1

V2

GND

25 nF

25 nF

H1SL+H1BL

66 pF

H2SL+H2BL

58 pF

H1SR+H1BR

66 pF

H2SR+H2BR

58 pF

20 pF

20 pF

GND

GND

Reset

10 pF

GND

SUB

2 nF

GND

FD

21 pF

5 nF