LM5037 datasheet(16/40 Pages) TI

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Time

CLK

OUTA

OUTB

tON(max)

tOSC

tDEAD

DEAD

OSC

RT1/SYNC

0.162

= ç

(

)

MAX

OSC

RT2

10-

= ç

DEAD

50 ns

250 ns

DEAD

RT2

= ç

LM5037

SNVS578D – NOVEMBER 2008 – REVISED MAY 2015

www.ti.com

Feature Description (continued)

(1)

(2)

(3)

The recommended dead-time range is between 50 ns and 250 ns. Beyond 250 ns, the RRT2 resistance becomes

excessively large, and is prone to noise pickup. Fixed internal delays limit the dead-time to greater than 50 ns.

After the dead-time has been programmed by RT2, the overall oscillator frequency can be set by selecting the

resistor RRT1/SYNC using Equation 4.

(4)

For example, if the desired oscillator frequency is 400 kHz (OUTA and OUTB each switching at 200 kHz) and

desired dead-time is 100 ns, the maximum duty cycle for each output is 96%. The value of RRT1/SYNC is 15 kΩ

and RRT2 is 20 kΩ.

Figure 15. Timing Diagram of OUTA, OUTB and Dead-Time Set by RT2

As shown in Figure 15, the internal clock pulse width is the same as the dead-time set by the RT2 pin. This

dead-time pulse is used to limit the maximum duty cycle for each of the outputs. Also, the discharge FET

connected to the RAMP pin is enabled during the dead-time every clock period. The voltages at both the

RT1/SYNC and RT2 pins are internally regulated to a nominal 2 V. Both the RRT1/SYNC and RRT2 resistors should

be located as close as possible to the device, and connected directly to the pins. Consider the tolerance of the

external resistors and the frequency tolerance indicated in the Electrical Characteristics table when determining

the worst case frequency range.

7.3.11 Synchronization Capability

The LM5037 device can be synchronized to an external clock by applying a narrow ac pulse to the RT1/SYNC

pin. The external clock must be at least 10% higher than the free-running oscillator frequency set by the

RRT1/SYNC and RRT2 resistors. If the external clock frequency is less than the programmed frequency, the device

ignores the synchronizing pulses. The synchronization pulse width at the RT1/SYNC pin must be a minimum of

15 ns wide. The synchronization signal should be coupled into the RT1/SYNC pin through a 100 pF capacitor or

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