AX5043 datasheet(16/47 Pages) ONSEMI

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AX5043

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CIRCUIT DESCRIPTION

The AX5043 is a true single chip ultra−low power

narrow−band CMOS transceiver for use in licensed and

unlicensed bands from 27 and 1050 MHz. The on−chip

transceiver consists of a fully integrated RF front−end with

modulator, and demodulator. Base band data processing is

implemented in an advanced and flexible communication

controller that enables user friendly communication via the

SPI interface.

AX5043 can be operated from a 1.8 V to 3.6 V power

supply over a temperature range of −40

°C to 85°C. It

consumes 7 − 48 mA for transmitting at 868 MHz carrier

frequency, 4 – 51 mA for transmitting at 169 MHz

depending on the output power. In receive operation AX

5043 consumes 9 − 11 mA at 868 MHz carrier frequency and

6.5 − 8.5 mA at 169 MHz.

The AX5043 features make it an ideal interface for

integration into various battery powered solutions such as

ticketing or as transceiver for telemetric applications e.g. in

sensors. As primary application, the transceiver is intended

for UHF radio equipment in accordance with the European

Telecommunication Standard Institute (ETSI) specification

EN 300 220−1 and the US Federal Communications

Commission (FCC) standard Title 47 CFR Part 15 as well as

Part 90. AX5043 is compliant with respective narrow−band

regulations. Additionally AX5043 is suited for systems

targeting compliance with Wireless M−Bus standard EN

13757−4:2005. Wireless M−Bus frame support (S, T, R) is

built−in.

AX5043 supports any data rate from 0.1 kbps to 125 kbps

for FSK, 4−FSK, GFSK, GMSK, MSK, ASK and PSK. To

achieve optimum performance for specific data rates and

modulation schemes several register settings to configure

the AX5043 are necessary, for details see the AXSEM

RadioLab Software which calculates the necessary register

settings and the AX5043 Programming Manual.

The AX5043 can be operated in two fundamentally

different modes.

In frame mode data is sent and received via the SPI port

in frames. Pre− and post−ambles as well as checksums can

be generated automatically. Interrupts control the data flow

between a micro−controller and the AX5043.

In wire mode the IC behaves as an extension of any wire.

The internal communication controller is disabled and the

modem data is directly available on a dedicated pin (DATA).

The bit clock is also output on a dedicated pin (DCLK). In

this mode the user can connect the data pin to any port of a

micro−controller or to a UART, but has to control coding,

checksums, pre and post ambles. The user can choose

between synchronous and asynchronous wire mode,

asynchronous wire mode performs RS232 start bit

recognition and re−synchronization for transmit.

Both modes can be used both for transmit and receive. In

both cases the AX5043 behaves as a SPI slave interface.

Configuration of the AX5043 is always done via the SPI

interface.

The receiver and the transmitter support multi−channel

operation for all data rates and modulation schemes.

Voltage Regulators

The AX5043 uses an on−chip voltage regulator system to

create stable supply voltages for the internal circuitry from

the primary supply VDD_IO. The I/O level of the digital

pins is VDD_IO.

Pins VDD_ANA are supplied for external decoupling of

the power supply used for the on−chip PA.

The voltage regulator system must be set into the

appropriate state before receive or transmit operations can

initiated.

This

handled

automatically

when

programming the device modes via the PWRMODE

to check if the regulated voltages are ready (bit SVIO) or if

VDD_IO has dropped below the brown−out level of 1.3V

(bit SSUM).

In power−down mode the core supply voltages for digital

and analog functions are switched off to minimize leakage

power. Most register contents are preserved but access to the

FIFO is not possible and FIFO contents are lost. SPI access

to registers is possible, but at lower speed.

In deep−sleep mode all supply voltages are switched off.

All digital and analog functions are disabled. All register

contents are lost. To leave deep−sleep mode the pin SEL has

to be pulled low. This will initiate startup and reset of the

AX5043. Then the MISO line should be polled, as it will be

held low during initialization and will rise to high at the end

of the initialization, when the chip becomes ready for

operation.

Crystal Oscillator and TCXO Interface

The AX5043 is normally operated with an external

TCXO, which is required by most narrow−band regulation

with a tolerance of 0.5 ppm to 1.5 ppm depending on the

regulation. The on−chip crystal oscillator allows the use of

an inexpensive quartz crystal as the RF generation

subsystem’s timing reference when possible from a

regulatory point of view.

A wide range of crystal frequencies can be handled by the

crystal oscillator circuit. As the reference frequency impacts

both the spectral performance of the transmitter as well as

the current consumption of the receiver, the choice of

reference frequency should be made according to the

regulatory regime targeted by the application. For

guidelines see the separate Application Notes for usage of

AX5043 in compliance with various regulatory regimes.

The crystal or TCXO reference frequency should be

chosen so that the RF carrier frequency is not an integer

multiple of the crystal or TCXO frequency.

The oscillator circuit is enabled by programming the

PWRMODE register. At power−up it is enabled.

AX5043 Datasheet(PDF) 16 Page - ON Semiconductor

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