DAP041 datasheet(28/40 Pages) ONSEMI

28 / 40 page

SCY99194

http://onsemi.com

Figure 55. Skip Mode Timing Diagram

Clamped Driver

The supply voltage for the SCY99194 can be as high as

28 V, but most of the MOSFETs that will be connected to the

DRV pin cannot accept more than 20 V on their gate. The

driver pin is therefore clamped safely below 16 V. This

driver has a typical capability of 500 mA for source current

and 800 mA for sink current.

Current−Mode Control With Slope Compensation and

Soft−Start

SCY99194 is a current−mode controller, which means

that the FB voltage sets the peak current flowing in the

inductance and the MOSFET. This is done through a PWM

comparator: the current is sensed across a resistor and the

resulting voltage is applied to the CS pin. It is applied to one

input of the PWM comparator through a 250 ns LEB block.

On the other input the FB voltage divided by 5 sets the

threshold: when the voltage ramp reaches this threshold, the

output driver is turned off. The maximum value for the

current sense is 0.7 V, and it is set by a dedicated comparator.

Each time the controller is starting, i.e. the controller was

off and starts – or restarts – when VCC reaches VCC(on), a

soft−start is applied: the current sense setpoint is increased

by 15 discrete steps from 0 (the minimum level can be

higher than 0 because of the LEB and propagation delay)

until it reaches VILIM (after a duration of tSSTART), or until

the FB loop imposes a setpoint lower than the one imposed

by the soft−start (the two comparators outputs are OR’ed).

DAP041 Datasheet(PDF) 28 Page - ON Semiconductor