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SM5842AP Datasheet(PDF) 19 Page - Nippon Precision Circuits Inc |
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SM5842AP Datasheet(HTML) 19 Page - Nippon Precision Circuits Inc |
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19 / 23 page  SM5842AP/APT NIPPON PRECISION CIRCUITS—19 Data Input to Output Delay Timing This is the digital filter arithmetic computation time from the completion of data input at rate fs (tINPUT) on the rising edge of LRCI to the start of data output at rate 8fs (tOUTPUT) on the falling edge of WCKO. Table 7. Output delay CKSLN SYNCN Mode tOUTPUT − tINPUT LOW (256fs) LOW After reset + sync mode 48.625/fs HIGH Jitter-free mode 48.25/fs − 49.0/fs HIGH (384fs) LOW After reset + sync mode 48.75/fs HIGH Jitter-free mode 48.375/fs − 49.125/fs Figure 10. Delay timing 1 Figure 11. Delay timing 2 48/fs 1/fs Serial data Input tINPUT tOUTPUT Serial data output tOUTPUT Serial data output WCKO (256fs) WCKO (384fs) LRCI tOUTPUT tOUTPUT−tINPUT tINPUT |
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