LM95241 datasheet(6/30 Pages) TI

6 / 30 page

LM95241

SNIS143E – AUGUST 2006 – REVISED MARCH 2013

www.ti.com

Logic Electrical Characteristics Digital DC Characteristics

Unless otherwise noted, these specifications apply for VDD=+3.0 to 3.6 Vdc. Boldface limits apply for TA = TJ = TMIN to

TMAX; all other limits TA= TJ=+25°C, unless otherwise noted.

Symbol

Parameter

Conditions

Typical(1)

Limits(2)

Units

(Limit)

SMBDAT, SMBCLK INPUTS

VIN(1)

Logical “1” Input Voltage

2.1

V (min)

VIN(0)

Logical “0”Input Voltage

0.8

V (max)

VIN(HYST)

SMBDAT and SMBCLK Digital Input

400

Hysteresis

IIN(1)

Logical “1” Input Current

VIN = VDD

0.005

±10

µA (max)

IIN(0)

Logical “0” Input Current

VIN = 0 V

−0.005

±10

µA (max)

CIN

Input Capacitance

SMBDAT OUTPUT

IOH

High Level Output Current

VOH = VDD

µA (max)

VOL

SMBus Low Level Output Voltage

IOL = 4mA

0.4

V (max)

IOL = 6mA

0.6

(1)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(2)

Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

Logic Electrical Characteristics SMBus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for VDD=+3.0 Vdc to +3.6 Vdc, CL (load capacitance) on output lines = 80

pF. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25°C, unless otherwise noted.

The switching characteristics of the LM95241 fully meet or exceed the published specifications of the SMBus version 2.0. The

following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95241. They

adhere to but are not necessarily the SMBus bus specifications.

Symbol

Parameter

Conditions

Typical(1)

Limits(2)

Units

(Limit)

fSMB

SMBus Clock Frequency

100

kHz (max)

kHz (min)

tLOW

SMBus Clock Low Time

from VIN(0)max to VIN(0)max

4.7

µs (min)

ms (max)

tHIGH

SMBus Clock High Time

from VIN(1)min to VIN(1)min

4.0

µs (min)

tR,SMB

SMBus Rise Time

See(3)

µs (max)

tF,SMB

SMBus Fall Time

See(4)

0.3

µs (max)

tOF

Output Fall Time

CL = 400pF,

250

ns (max)

IO = 3mA

(4)

tTIMEOUT

SMBDAT and SMBCLK Time Low for Reset of

ms (min)

Serial Interface(5)

ms (max)

tSU;DAT

Data In Setup Time to SMBCLK High

250

ns (min)

tHD;DAT

Data Out Stable after SMBCLK Low

300

ns (min)

1075

ns (max)

tHD;STA

Start Condition SMBDAT Low to SMBCLK Low

100

ns (min)

(Start condition hold before the first clock falling

edge)

tSU;STO

Stop Condition SMBCLK High to SMBDAT Low

100

ns (min)

(Stop Condition Setup)

tSU;STA

SMBus Repeated Start-Condition Setup Time,

0.6

µs (min)

SMBCLK High to SMBDAT Low

(1)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(2)

Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

(3)

The output rise time is measured from (VIN(0)max + 0.15V) to (VIN(1)min − 0.15V).

(4)

The output fall time is measured from (VIN(1)min - 0.15V) to (VIN(1)min + 0.15V).

(5)

Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM95241's SMBus state machine,

therefore setting SMBDAT and SMBCLK pins to a high impedance state.

Submit Documentation Feedback

Product Folder Links: LM95241

LM95241 Datasheet(PDF) 6 Page - Texas Instruments

LM95241 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Datasheet Download

Link URL