L8708H datasheet(50/66 Pages) ZILOG

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Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

P R E L I M I N A R Y

DS96LV00800

SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR

controls a Divide-by-16 prescaler of SCLK/TCLK. The pur-

pose of this control is to selectively reduce device power

consumption during normal processor execution (SCLK

control) and/or HALT mode (where TCLK sources interrupt

logic). After Stop-Mode Recovery, this bit is set to a 0.

Stop-Mode Recovery Source (D2, D3, and D4). These

three bits of the SMR specify the wake up source of the

STOP recovery (Figure 41 and Table 7).

Note: Any Port 2 bit defined as an output will drive the cor-

responding input to the default state to allow the remaining

inputs to control the AND/OR function. Refer to SMR2 reg-

ister for other recover sources.

Stop-Mode Recovery Delay Select (D5). This bit, if low,

disables the 5 ms /RESET delay after Stop-Mode Recov-

ery. The default configuration of this bit is one. If the "fast"

wake up is selected, the Stop-Mode Recovery source

needs to be kept active for at least 5TpC.

Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-

sition indicates that a High level on any one of the recovery

sources wakes the Z86LXX from STOP mode. A 0 indi-

cates Low level recovery. The default is 0 on POR (Figure

36).

Cold or Warm Start (D7). This bit is set by the device

upon entering STOP mode. It is a Read Only Flag bit. A 1

in D7 (warm) indicates that the device will awaken from a

SMR source or a WDT while in STOP mode. A 0 in this bit

(cold) indicates that the device will be reset by a POR,

WDT while not in STOP, or the device awakened from a

low voltage standby mode.

Stop-Mode Recovery Register 2 (SMR2). This register

determines the mode of Stop-Mode Recovery for SMR2

Figure 42).

If SMR2 is used in conjunction with SMR, either of the

specified events will cause a Stop-Mode Recovery.

Note: Port pins configured as outputs are ignored as a

SMR or SMR2 recovery source. For example, if the NAND

or P23-P20 is selected as the recovery source and P20 is

configured as an output then the remaining SMR pins

(P23-P21) form the NAND equation.

Table 7. Stop-Mode Recovery Source

SMR:432

Operation

Description of Action

POR and/or external reset

recovery

Reserved

P31 transition

P32 transition

P33 transition

P27 transition

Logical NOR of P20

through P23

Logical NOR of P20

through P27

L8708H Datasheet(PDF) 50 Page - Zilog, Inc.

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