| Electronic Components Datasheet Search |
|
Z89136 Datasheet(PDF) 3 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z89136 Datasheet(HTML) 3 Page - Zilog, Inc. |
|
3 / 66 page ![]() Z89135/136 (ROMless) Zilog Low-Cost DTAD Controller DS97TAD0300 P R E L I M I N A R Y 1-3 1 Z8 Core Processor The Z8 is Zilog’s 8-bit MCU core with an Expanded Regis- ter File to allow access to register-mapped peripheral and I/O circuits. The Z8® MCU offers a flexible I/O scheme, an efficient register and address space structure, and a num- ber of ancillary features. For applications demanding powerful I/O capabilities, the Z89135/136 offers 47 pins dedicated to input and output. These lines are grouped into six ports. Each port is config- urable under software control to provide timing, status sig- nals and parallel I/O with or without handshake. There are four basic memory resources for the Z8 that are available to support a wide range of configurations: Pro- gram Memory, Register File, Data Memory, and Expanded Register File. The Z8 core processor is characterized by an efficient register file that allows any of 256 on-board data and control registers to be the source and/or the des- tination of almost any instruction. Traditional microproces- sor accumulator bottlenecks are eliminated. The Register File is composed of 236 bytes of general-pur- pose registers, four I/O port register,s and 15 control and status registers. The Expanded Register File consists of mailbox registers, WDT mode register, DSP Control regis- ter, Stop-Mode Recovery register, Port Configuration reg- ister, and the control and data registers for Port 4 and Port 5. To unburden the software from supporting the real-time problems, such as counting/timing and data communica- tion, the Z8 offers two on-chip counter/timers with a large number of user selectable modes. Watch-Dog Timer and Stop-Mode Recovery features are software driven by setting specific bits in control registers. STOP and HALT instructions support reduced power op- eration. The low power STOP Mode allows parameter in- formation to be stored in the register file if power fails. An external capacitor or battery retains power to the device. DSP Coprocessor The DSP coprocessor is a second generation, 16-bit two’s complement CMOS Digital Signal Processor (DSP). Most instructions, including multiply and accumulate, are ac- complished in a single clock cycle. The processor contains two on-chip data RAM blocks of 256 words, a 6K word pro- gram ROM, 24-bit ALU, 16 x 16 multiplier, 24-bit Accumu- lator, shifter, six-level stack, three vectored interrupts, and two inputs for conditional program jumps. Each RAM block contains a set of four pointers which may be incremented or decremented automatically to affect hardware looping without software overhead. The data RAMs can be simul- taneously addressed and loaded to the multiplier for a true single cycle scalar multiply. Four external DSP registers are mapped into the expand- ed register file of the Z8. Communication between the Z8 and the DSP occurs through those common registers which form the mailbox registers. The analog signal is generated by a 10-bit resolution Pulse Width Modulator. The PWM output is a digital signal with CMOS output levels. The output signal has a resolution of 1 in 1024 with a sampling rate of 16 kHz (XTAL = 20.48 MHz). The sampling rate can be changed under software control and can be set at 4, 10, 16, and 64 kHz. The dy- namic range of the PWM is from 0 to 4V. An 8-bit resolution half-flash A/D converter is provided. The conversion is conducted with a sampling frequency of 8, 16, 32, 64, or 128 kHz. (XTAL = 20.48 MHz) in order to provide oversampling. The input signal is 4V peak to peak. Scaling is normally ±1.25V for the 2.5V peak to peak off- set. Two additional timers (Timer2 and Timer3) have been added to support different sampling rates for the A/D and D/A converters. These timers are free running counters that divide the crystal frequency to the appropriate sam- pling of frequency. Notes: All signals with a preceding front slash, "/", are ac- tive Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions be- low: Connection Circuit Device Power VCC VDD Ground GND VSS |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |