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Z89136 Datasheet(PDF) 49 Page - Zilog, Inc. |
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Z89136 Datasheet(HTML) 49 Page - Zilog, Inc. |
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49 / 66 page ![]() Z89135/136 (ROMless) Zilog Low-Cost DTAD Controller DS97TAD0300 P R E L I M I N A R Y 1-49 1 ANALOG CONTROL REGISTER (ACR) The Analog Control register is mapped to register EXT6 of the DSP (Table 15). This read/write register is accessible by the DSP only. The 16-bit field of EXT6 defines modes of both the A/D and the D/A. The High Byte configures the D/A, while the Low Byte controls the A/D mode. Table 15. EXT6 Analog Control Register (ACR) Field Position Attrib Value Label MPX_DSP_INT0 f--------------- R/W 1 0 P26 Timer3 Reserved -edcb----------- R W Return “0” No Effect D/A_SamplingRate -----a98-------- R/W 11x 101 100 010 011 001 000 Reserved Reserved 64 kHz 16 kHz 10 kHz 4 kHz Reserved DSP_port --------76------ R/W User defined DSP Outputs Enable A/D ----------5----- R/W 1 0 A/D Enabled A/D Disabled ConversionDone -----------4---- W R1 0 No effect Done Not Done StartConversion ------------3--- R/W 1 0 Start Wait Timer A/D_SamplingRate -------------210 R/W 11x 101 100 010 011 001 000 Reserved Reserved 128 kHz 64 kHz 32 kHz 16 kHz 8 kHz |
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