UPSD3312D datasheet(50/272 Pages) STMICROELECTRONICS

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UPSD33xx instruction set summary

UPSD33xx

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Doc ID 9685 Rev 7

UPSD33xx instruction set summary

Table 6, Table 7, Table 8, Table 9, Table 10, and Table 11 list all of the instructions supported

by the UPSD33xx, including the number of bytes and number of machine cycles required to

implement each instruction. This is the standard 8051 instruction set.

The meaning of “machine cycles” is how many 8032 MCU core machine cycles are required

to execute the instruction. The “native” duration of all machine cycles is set by the memory

wait state settings in the SFR, BUSCON, and the MCU clock divider selections in the SFR,

CCON0 (i.e. a machine cycle is typically set to 4 MCU clocks for a 5 V UPSD33xx).

However, an individual machine cycle may grow in duration when either of two things

happen:

Astall is imposed while loading the 8032 Pre-Fetch Queue (PFQ); or

The occurrence of a cache miss in the Branch Cache (BC) during a branch in program

execution flow.

See Section 5: 8032 MCU core performance enhancements on page 32 or more details.

But generally speaking, during typical program execution, the PFQ is not empty and the BC

has no misses, producing very good performance without extending the duration of any

machine cycles.

The UPSD33xx programmers guide describes each instruction operation in detail.

Table 6.

Arithmetic instruction set

Mnemonic(1)

and use

Description

Length/cycles

ADD

A, Rn

Add register to ACC

1 byte/1 cycle

ADD

A, Direct

Add direct byte to ACC

2 byte/1 cycle

ADD

A, @Ri

Add indirect SRAM to ACC

1 byte/1 cycle

ADD

A, #data

Add immediate data to ACC

2 byte/1 cycle

ADDC

A, Rn

Add register to ACC with carry

1 byte/1 cycle

ADDC

A, direct

Add direct byte to ACC with

carry

2 byte/1 cycle

ADDC

A, @Ri

Add indirect SRAM to ACC

with carry

1 byte/1 cycle

ADDC

A, #data

Add immediate data to ACC

with carry

2 byte/1 cycle

SUBB

A, Rn

Subtract register from ACC

with borrow

1 byte/1 cycle

SUBB

A, direct

Subtract direct byte from ACC

with borrow

2 byte/1 cycle

SUBB

A, @Ri

Subtract indirect SRAM from

ACC with borrow

1 byte/1 cycle

SUBB

A, #data

Subtract immediate data from

ACC with borrow

2 byte/1 cycle

INC

Increment A

1 byte/1 cycle

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