TMP102 datasheet(5/29 Pages) TI1

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TMP102-Q1

www.ti.com

SBOS702C – OCTOBER 2014 – REVISED DECEMBER 2015

6.6 Timing Requirements

see the Timing Diagrams section for additional information

HIGH-SPEED

FAST MODE

MODE

UNIT

MIN

MAX

MIN

MAX

ƒ(SCL)

SCL operating frequency

V+

0.001

0.4

0.001

2.85

MHz

Bus-free time between STOP and START

t(BUF)

600

160

condition

Hold time after repeated START condition.

t(HDSTA)

600

160

After this period, the first clock is generated.

See Two-Wire Timing Diagrams.

t(SUSTA)

repeated start condition setup time

600

160

t(SUSTO)

STOP Condition Setup Time

600

160

t(HDDAT)

Data hold time

100

900

105

t(SUDAT)

Data setup time

100

V+ , see Two-Wire Timing

t(LOW)

SCL-clock low period

1300

210

Diagrams

t(HIGH)

SCL-clock high period

See Two-Wire Timing Diagrams

600

tFD

Data fall time

See Two-Wire Timing Diagrams

300

See Two-Wire Timing Diagrams

300

tRD

Data rise time

SCLK

≤ 100 kHz, see Two-Wire

1000

Timing Diagrams

tFC

Clock fall time

See Two-Wire Timing Diagrams

300

tRC

Clock rise time

See Two-Wire Timing Diagrams

300

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