TMP102-Q1

SBOS702C – OCTOBER 2014 – REVISED DECEMBER 2015

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7.3.4 Serial Bus Address

To communicate with the TMP102-Q1 device, the master must first address slave devices through a slave

address byte. The slave address byte consists of seven address bits and a direction bit indicating the intent of

executing a read or write operation.

The TMP102-Q1 device features an address pin to allow up to four devices to be addressed on a single bus.

Table 4 lists the pin-logic levels used to properly connect up to four devices.

Table 4. Address Pin and Slave Addresses

DEVICE TWO-WIRE ADDRESS

A0 PIN CONNECTION

1001000

Ground

1001001

V+

1001010

SDA

1001011

SCL

7.3.5 Writing and Reading Operation

Accessing a particular register on the TMP102-Q1 device is accomplished by writing the appropriate value to the

pointer register. The value for the pointer register is the first byte transferred after the slave address byte with the

R/W bit low. Every write operation to the TMP102-Q1 device requires a value for the pointer register (see

Figure 9).

When reading from the TMP102-Q1 device, the last value stored in the pointer register by a write operation

determines which register is read by a read operation. To change the register pointer for a read operation, a new

value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the

R/W bit low, followed by the pointer register byte. No additional data are required. The master then generates a

START condition and sends the slave address byte with the R/W bit high to initiate the read command. See

Figure 10 for details of this sequence. If repeated reads from the same register are desired, continuously sending

the pointer register bytes is not required because the TMP102-Q1 device remembers the pointer register value

until the value is changed by the next write operation.

Register bytes are sent with the most significant byte first, followed by the least significant byte.

7.3.6 Slave Mode Operations

The TMP102-Q1 device operates either as a slave receiver or a slave transmitter. As a slave device, the

TMP102-Q1 device never drives the SCL line.

7.3.6.1 Slave Receiver Mode

The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP102-Q1 then

acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The

TMP102-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the

register addressed by the pointer register. The TMP102-Q1 acknowledges reception of each data byte. The

master can terminate data transfer by generating a START or STOP condition.

7.3.6.2 Slave Transmitter Mode

The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges

reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of

the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The

master terminates data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a

START or STOP condition.

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