Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

Frame4DataByte2

1

StartBy

Master

ACKBy

Device

ACKBy

Device

ACKBy

Device

StopBy

Master

1

9

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

Frame3DataByte1

ACKBy

Device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

0

A1

(1)

A0

(1)

R/W

0

0

0

0

0

0

P1

P0

¼

¼

NOTE:(1)ThevalueofA0andA1aredeterminedbytheADD0pin.

SCL

SDA

t

(LOW)

t

RC

t

FC

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

t

RD

t

FD

TMP102-Q1

SBOS702C – OCTOBER 2014 – REVISED DECEMBER 2015

www.ti.com

Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that

acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that

the SDA line is stable low during the high period of the Acknowledge clock pulse. Setup and hold

times must be taken into account. On a master receive, the termination of the data transfer can be

signaled by the master generating a not-acknowledge (1) on the last byte that has been transmitted

by the slave.

7.3.12 Two-Wire Timing Diagrams

Figure 8. Two-Wire Timing Diagram

Figure 9. Two-Wire Timing Diagram for Write Word Format

12

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