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Data Sheet

AD7915/AD7916

Rev. 0 | Page 13 of 26

THEORY OF OPERATION

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

16,384C

32,768C

LSB

SW+

MSB

LSB

SW–

MSB

16,384C

32,768C

IN+

REF

GND

IN–

Figure 28. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7915/AD7916 are high speed, low power, single-supply,

precise, 16-bit ADCs that use a successive approximation

architecture.

The AD7916 can convert 500,000 samples per second

(500 kSPS), whereas the AD7915 can convert 1,000,000 samples

per second (1 MSPS); both devices power down between con-

versions. When operating at 1 MSPS, the AD7915 typically

consumes 7 mW, making the ADC ideal for battery-powered

applications.

The AD7915/AD7916 provide the user with an on-chip track-

and-hold amplifier and do not exhibit any pipeline delay or

latency, making these devices ideal for multiple multiplexed

channel applications.

The AD7915/AD7916 can be interfaced to any 1.8 V to 5 V

digital logic family. They are available in a 10-lead MSOP or a

tiny 10-lead LFCSP that allows space savings and flexible

configurations.

CONVERTER OPERATION

The AD7915/AD7916 are a successive approximation ADCs

based on a charge redistribution digital-to-analog converter

(DAC). Figure 28 shows the simplified schematic of the ADC.

The capacitive DAC consists of two identical arrays of 18

binary-weighted capacitors, which are connected to the two

comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via SW+ and

SW−. All independent switches are connected to the analog

inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. When the acquisition phase is complete and the CNV

input goes high, a conversion phase is initiated.

When the conversion phase begins, SW+ and SW− are opened

first. The two capacitor arrays are then disconnected from the

inputs and connected to the GND input. Therefore, the

differential voltage between the IN+ and IN− inputs captured at

the end of the acquisition phase is applied to the comparator

inputs, causing the comparator to become unbalanced. By

switching each element of the capacitor array between GND

and REF, the comparator input varies by binary-weighted

voltage steps (VREF/2, VREF/4 ... VREF/65,536). The control logic

toggles these switches, starting with the MSB, to bring the

comparator back into a balanced condition. After the

completion of this process, the device returns to the acquisition

phase, and the control logic generates the ADC output code.

Because the AD7915/AD7916 have an on-board conversion

clock, the serial clock, SCK, is not required for the conversion

process.

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