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Data Sheet

AD7915/AD7916

Rev. 0 | Page 19 of 26

CS MODE, 4-WIRE, WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7915/AD7916

devices are connected to an SPI-compatible digital host.

A connection diagram example using two AD7915/AD7916

devices is shown in Figure 39, and the corresponding timing is

given in Figure 40.

With SDI high, a rising edge on CNV initiates a conversion,

selects SDI/CS mode, and forces SDO to high impedance. In

this mode, CNV must be held high during the conversion phase

and the subsequent data read back; if SDI/CS and CNV are low,

SDO is driven low. Prior to the minimum conversion time,

SDI/CS can be used to select other SPI devices, such as analog

multiplexers, but SDI/CS must be returned high before the

minimum conversion time elapses and then held high for the

maximum possible conversion time. When the conversion is

complete, the AD7915/AD7916 enter the acquisition phase and

power down. Each ADC result can be read by bringing its SDI/CS

input low, which consequently outputs the MSB onto SDO. The

remaining data bits are then clocked by subsequent SCK falling

edges. The data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the SCK

falling edge allows a faster reading rate, provided that it has an

acceptable hold time. After the 16th SCK falling edge or when

SDI/CS goes high (whichever occurs first), SDO returns to high

impedance and another AD7915/AD7916 can be read.

AD7915/

AD7916

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7915/

AD7916

SDO

CNV

SCK

SDI/CS

Figure 39. CS Mode Without Busy Indicator, 4-Wire Connection Diagram

SDO

D15

D14

D13

tDIS

SCK

tHSDO

tDSDO

tEN

CONVERSION

ACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

CNV

tSSDICNV

tHSDICNV

tSCK

tSCKL

tSCKH

D15

D14

SDI/CS (CS1)

SDI/CS (CS2)

Figure 40. CS Mode Without Busy Indicator, 4-Wire Serial Interface Timing

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