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AD7915/AD7916

Data Sheet

Rev. 0 | Page 16 of 26

20Ω

10µF

100nF

+2.5V

+5V REF

+5.2V

–0.2V

±10V,

±5V, ..

REF

VDD

GND

IN+

IN–

AD7915/

AD7916

2.7nF

ADA4941-1

OUT+

OUT–

REF

100nF

Figure 33. Single-Ended to Differential Driver Circuit

SINGLE TO DIFFERENTIAL DRIVER

For applications using a single-ended analog signal, either bipolar

or unipolar, the ADA4941-1 single-ended to differential driver

allows a differential input to the device. The schematic is shown in

Figure 33. The ADA4940-1, which is a fully differential amplifier,

can be used as a single-ended to-differential driver as well.

R1 and R2 set the attenuation ratio between the input range and

the ADC range (VREF). R1, R2, and CF are chosen depending on

the desired input resistance, signal bandwidth, antialiasing, and

noise contribution. For example, for the ±10 V range with a 4 kΩ

impedance, R2 = 1 kΩ and R1 = 4 kΩ.

R3 and R4 set the common mode on the IN− input, and R5 and R6

set the common mode on the IN+ input of the ADC. Make sure

that the common mode is close to VREF/2. For example, for the

±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ,

R5 = 10.5 kΩ, and R6 = 9.76 kΩ.

VOLTAGE REFERENCE INPUT

The AD7915/AD7916 voltage reference input, REF, has a

dynamic input impedance and must, therefore, be driven by a

low impedance source with efficient decoupling between the

REF and GND pins, as explained in the Layout section.

When REF is driven by a very low impedance source (for

example, a reference buffer using the AD8031, ADA4805-1 or

the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is

appropriate for optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43

3 reference.

If desired, a reference decoupling capacitor with values as small

as 2.2 μF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value ceramic

decoupling capacitor (for example, 100 nF) between the REF

and GND pins.

POWER SUPPLY

The AD7915/AD7916 use two power supply pins: a core supply

(VDD) and a digital input/output interface supply (VIO). VIO

allows direct interface with any logic between 1.8 V and 5.5 V. To

reduce the number of supplies needed, VIO and VDD can be

tied together. The AD7915/AD7916 are independent of power

supply sequencing between VIO and VDD. Additionally, they are

insensitive to power supply variations over a wide frequency

range, as shown in Figure 34.

10k

100k

FREQUENCY (Hz)

Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency

The AD7915/AD7916 power down automatically at the end of

each conversion phase.

DIGITAL INTERFACE

Although the AD7915/AD7916 have a reduced number of pins,

they offer flexibility in their serial interface modes.

When in CS mode, the AD7915/AD7916 are compatible with

SPI, QSPI™, MIRCROWIRE™, digital hosts, and DSPs. In this

mode, the AD7915/AD7916 can use either a 3-wire or 4-wire

interface. A 3-wire interface using the CNV, SCK, and SDO

signals minimizes wiring connections, which is useful, for

instance, in isolated applications. A 4-wire interface using the

SDI/CS, CNV, SCK, and SDO signals allows CNV, which initiates

the conversions, to be independent of the readback timing (SDI).

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