ADS5560 datasheet(36/61 Pages) TI1

36 / 61 page

ADS5560, ADS5562

SLWS207B – MAY 2008 – REVISED JANUARY 2016

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Programming (continued)

Table 2. Parallel Pin Definition

CONTROL MODES

DFS

DATA FORMAT and the LVDS/CMOS output interface

MODE

Internal or external reference

SEN

CLKOUT edge programmability

SCLK

LOW SPEED mode control for low sampling frequencies (

≤ 30 MSPS)

SDATA

STANDBY mode – Global (ADC, internal references and output buffers are powered down)

7.5.2.1 Using Serial Interface Programming Only

To program using the serial interface, the internal registers must first be reset to the default values, and the

RESET pin must be kept low. In this mode, the SEN, SDATA, and SCLK pins function as serial interface pins

and are used to access the internal registers of ADC. The registers are reset either by applying a pulse on the

RESET pin (of width greater than 10 ns), or by a high setting on the <RST> bit (D1 in register 0x6C). The Serial

Interface section describes the register programming and register reset in more detail.

Because the parallel pins, DFS and MODE, are not used in this mode, they must be tied to ground.

7.5.2.2 Using Both Serial Interface And Parallel Controls

For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE) can

also be used to configure the device.

The serial registers must first be reset to the default values and the RESET pin must be kept low. In this mode,

the SEN, SDATA, and SCLK pins function as serial interface pins and are used to access the internal registers of

ADC. The registers are reset either by applying a pulse on RESET pin or by a high setting on the <RST> bit (D1

in register 0x6C). The Serial Interface section describes the register programming and register reset in more

detail.

The parallel interface control pins, DFS and MODE, are used and their function is determined by the appropriate

voltage levels as described in Table 7 and Table 8. The voltage levels are derived by using a resistor string as

shown in Figure 57. Because some functions are controlled using both the parallel pins and serial registers, the

priority between the two is determined by a priority table (Table 3).

Table 3. Priority Between Parallel Pins and Serial Registers

FUNCTIONS SUPPORTED

PRIORITY

When using the serial interface, <REF> bit (register 0x6D, bit D4) controls this mode,

MODE

Internal and external reference

ONLY if the MODE pin is tied low.

When using the serial interface, <DF> bit (register 0x63, bit D3) controls this mode,

DATA FORMAT

ONLY if the DFS pin is tied low.

When using the serial interface, <ODI> bit (register 0x6C, bits D3-D4) controls the LVDS

DFS

or CMOS selection independent of the state of DFS pin, only if the <ODI> bit is not

LVDS and CMOS

programmed as 00. The DFS pin controls LVDS/CMOS selection if the <ODI> bit is

programmed as 00.

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