ADS5560 datasheet(49/61 Pages) TI1

49 / 61 page

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C001

ADS5560, ADS5562

www.ti.com

SLWS207B – MAY 2008 – REVISED JANUARY 2016

Typical Application (continued)

8.2.3 Application Curve

Figure 61 shows the SNR of the ADC as a function of clock jitter and input frequency for the ADS5562 device.

This plot of curves take into account the aperture jitter of the ADC, the number of bits of resolution, and the

thermal noise estimation so that the plot can be used to predict SNR for a given input frequency and external

clock jitter. Figure 61 then may be used to set the jitter requirement for the clocking solution for a given input

bandwidth and given design goal for SNR.

Figure 61. SNR vs Input Frequency and External Clock Jitter

9 Power Supply Recommendations

The device requires a 3.3-V nominal supply for AVDD. The device also requires a 3.3-V supply for DRVDD.

There are no specific sequence power-supply requirements during device power-up. AVDD, and DRVDD can

power up in any order. It is recommended that the analog supply be low noise, such as would be the case if each

analog supply was generated by its own linear regulator. The digital supply would be much more tolerant of

supply noise and a DC-DC switching supply could be suitable for DRVDD.

At each power-supply pin, a 0.1-

μF decoupling capacitor should be kept close to the device. A separate

decoupling capacitor group consisting of a parallel combination of 10-

μF, 1-μF, and 0.1-μF capacitors can be

kept close to the supply source.

10 Layout

10.1 Layout Guidelines

Figure 62 is a section of the layout of the ADS5562 that illustrates good layout practices for the clocking, analog

input, and digital outputs. In this example, the analog input enters from the left while the clocking enters from the

top, keeping the clock signal away from the analog signals so as to not allow coupling between the analog signal

and the clock signal. On the layout of the differential traces, note the symmetry of the trace routing between the

two sides of the differential signals.

The digital outputs are routed off to the right, so as to keep the digital signals away from the analog inputs and

away from the clock. Note the circuitous routing added to some of the LVDS differential traces but not to others;

this is the equalize the lengths of the routing across all of the LVDS traces so as to preserve the setup/hold

timing at the end of the digital signal routings. If the timing closure in the receiving device (such as an FPGA or

ASIC) has enough timing margin, then the circuitous routing to equalize trace lengths may not be necessary.

In addition, the solid gray areas are ground planes, providing more isolation between the clocking and the analog

inputs as well as between the clocking and the digital outputs.

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