ADS5560 datasheet(5/61 Pages) TI1

5 / 61 page

ADS5560, ADS5562

www.ti.com

SLWS207B – MAY 2008 – REVISED JANUARY 2016

Pin Functions - LVDS Mode (continued)

I/O

DESCRIPTION

NO.

NAME

D6_D7_M

Differential output data D6 and D7 multiplexed, complement

D6_D7_P

Differential output data D6 and D7 multiplexed, true

D8_D9_M

Differential output data D8 and D9 multiplexed, complement

D8_D9_P

Differential output data D8 and D9 multiplexed, true

Data Format Select input.

This pin sets the DATA FORMAT (2s complement or Offset binary) and the LVDS/CMOS output

DFS

mode type. See Table 7 for detailed information.

The pin has an internal 100-k

Ω pulldown resistor to DRGND.

1, 36

DRGND

Digital and output buffer ground

2, 35

DRVDD

Digital and output buffer supply

INP

Differential analog input

INM

Mode select input.

MODE

This pin selects the Internal or External reference mode. See Table 8 for detailed information.

The pin has an internal 100-k

Ω pulldown resistor to AGND.

—

Do not connect

Output buffer enable input, active high.

The pin has an internal 100-k

Ω pullup resistor to DRVDD.

OVR

Out-of-range indicator, CMOS level signal

Serial interface reset input.

When using the serial interface, the user should apply a high-going pulse on this pin to reset the

internal registers.

RESET

When the serial interface is not used, the user should tie RESET permanently high. (SCLK,

SDATA and SEN can be used as parallel pin controls).

The pin has an internal 100-k

Ω pulldown resistor to DRGND.

This pin functions as serial interface clock input when RESET is low.

It functions as LOW SPEED MODE control when RESET is tied high. See Table 4 for detailed

SCLK

information.

The pin has an internal 100-k

Ω pulldown resistor to DRGND.

This pin functions as serial interface data input when RESET is low.

It functions as STANDBY control pin when RESET is tied high.

SDATA

See Table 5 for detailed information.

The pin has an internal 100-k

Ω pulldown resistor to DRGND.

This pin functions as serial interface enable input when RESET is low.

It functions as CLKOUT edge programmability when RESET is tied high. See Table 6 for detailed

SEN

information.

The pin has an internal 100-k

Ω pullup resistor to DRVDD.

Internal reference mode – Common-mode voltage output.

VCM

I/O

External reference mode – Reference input. The voltage forced on this pin sets the internal

reference.

—

PAD

—

Connect the PAD to the ground plane. See the Exposed Thermal Pad section.

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