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TPL5000

SNAS628B – JULY 2013 – REVISED DECEMBER 2014

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10 Power Supply Recommendations

The TPL5000 requires a voltage supply within 2.7 V and 5.5 V. A multilayer, ceramic-bypass X7R capacitor of

0.1

μF between VDD and GND pin is recommended.

11 Layout

11.1 Layout Guidelines

The more sensitive pins of the TPL5000 are the digital input pins D0, D1, D2 to select the timer interval. It is

mandatory to connect them to VDD or GND through short traces avoiding series resistance. It is mandatory to

keep these pins far from traces of high frequency signals, such as clock or communication bus. Signal integrity of

WAKE, RSTn and TCAL signal is achieved reducing parasitic capacitance on the traces between the TPL5000

and the micro-controller. In the application where the watchdog feature is not used, the DONE pin is required to

be tied to TCAL pin.

11.2 Layout Example

Figure 10. PCB Layout

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