L7292 datasheet(35/60 Pages) STMICROELECTRONICS

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L7292

9.2.12

SEQCFG.DLY1CFG - Delay 1 configuration

Delay before/after power up sequence configuration.



0x0: no delay.



0x1: delay before POR rising edge.



0x2: delay before starting sequence.



0x3: delay before starting sequence and before POR rising edge.

9.2.13

SEQCFG.DLY1 - Delay 1

Delay before de-assert POR (if enabled) and before starting sequence (if enabled).

If SEQCFG Bit 7 = 0



0x0: 10 ms



0x1: 12 ms



0x2: 14 ms



0x3: 16 ms



0x4: 18 ms



0x5: 20 ms



0x6: 22 ms



0x7: 24 ms

If SEQCFG Bit 7 = 1



Delay1 = 8 ms

9.2.14

PSCFG.EUVM - external undervoltage mask

Mask external supply undervoltage fault.



0: undervoltage generates fault.



1: undervoltage does not generate fault.

9.2.15

PSCFG.IUVM - internal undervoltage mask

Mask internal supply undervoltage fault.



0: undervoltage generates fault.



1: undervoltage does not generate fault.

9.2.16

PSCFG.DEGL - deglitch

Digital deglitch filter time duration for regulator output voltage monitor



0x0: 0

s



0x1: 1

s



0x2: 2

s



0x3: 5

s

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