L7292 datasheet(42/60 Pages) STMICROELECTRONICS

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Buck regulator description

L7292

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DocID028601 Rev 1

SEQCFG.DLY1 - Delay 1 - delay before de-assert POR (if enabled) and before starting

sequence (if enabled)

If SEQCFG Bit 7 = 0



0x0: 10 ms



0x1: 12 ms



0x2: 14 ms



0x3: 16 ms



0x4: 18 ms



0x5: 20 ms



0x6: 22 ms



0x7: 24 ms

If SEQCFG Bit 7 = 1



Delay1 = 8 ms

At the power up two conditions have to be asserted before to enable the ON phase of

switching regulators.

LDO INT voltage = 1.8 V

SUP voltage ≥ 2.8 V

When these conditions are asserted the default conditions stored in the EEPROM are

performed.

During this phase the comparators related to each BUCKx and Vsupply track the output

voltage with the threshold defined by the regulator adjustment bits.

After the BUCKx, Vsupplyx, and LDO INT are good, a programmable reset delay timeout

begins. After the programmed delay, the POR pin is pulled high through the internal pull-up

resistor to VBUS enabling the entire functionalities.

The timing detail is as follows (based on the default soft-start order and delays programmed

in the EEPROM): when the last start-up of regulators has ended (BUCK2 is the last one in

soft-start sequence, by default), it starts the count of two Delay 2, and then the POR delay

count (Delay 1) begins.

This means that with the default settings (Dly 1 = 8 ms, Dly 2 = 0.5 ms), the POR is released

and starts to be pulled up through the internal resistor 9 ms after the end of the start-up

routine of the last regulator.

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