ST2100 datasheet(7/39 Pages) STMICROELECTRONICS

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ST2100

Main features



Configurable hardware engine for multiple HomePlug PHY and real-time MAC layers

–

HomePlug™ AV and 1.0 standards

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HomePlug Green PHY standard



Integrated analog front-end

–

Programmable gain amplifier: gain range -12 dB to 48 dB

–

ADC and DAC

–

2.5 V voltage regulator

–

Zero crossing (ZC) comparator



ARM926EJ-S™ 32-bit RISC CPU up to 333 MHz

–

16 Kbyte if instruction cache, 16 Kbyte of data cache

–

32 Kbyte of instruction TCM and 16 Kbyte of data TCM

–

Three instruction sets: 32-bit for high performance, 16-bit (Thumb®) for efficient

code density, bytecode Java™ mode (Jazelle™) for direct execution of Java code

–

AMBA™ bus interface with fMAX 166 MHz



48 Kbyte on-chip boot ROM



8 Kbyte on-chip SRAM



8/16 bit DDR mobile at 166 MHz and DDR2 at 333 MHz memory controller



Serial memory interface



8/16-bits NOR Flash/NAND Flash and SRAM memory controller



Boot capability from NAND Flash, serial/parallel NOR Flash, and UART



Multichannel DMA controller (8 FIFOs and 16 dedicated channels)



Ethernet 10/100 MAC with MII interface (IEEE 802.3), RevMII, IEEE 802.1-AS and

802.1-Qav for audio video (AV) traffic



USB 2.0 (high-full-low speed) port with an integrated PHY able to work as a host or

device



PCI Express GEN1 (PCI Express standard version 1.1), single lane X1 dual mode

(both “Root Complex” and “Endpoint” modes supported), the PHY is a standard

8-bit/16-bit PIPE PHY interface. This peripheral supports also the serial ATA compliant

with the SATA/150.



Color LCD controller (up to 1024 x 768 resolution at 24 bpp true color, STN/TFT display

panels)



JPEG codec accelerator (1 clock/pixel)



Cryptographic coprocessor (DMA based programmable engine) with support for:

–

Advanced encryption standard (AES) cipher (128, 192, 256 bit keys) in ECB,

CBC, CTR modes

–

Data encryption standard (DES) and triple DES (TDES) cipher in ECB and CBC

modes

–

SHA-1, HMAC-SHA-1, SHA-256, HMAC-SHA-256, MD5, HMAC-MD5 digests



Up to 40 GPIOs (multiplexed with peripheral I/Os), all the I/Os have interrupt capability,

24 application specific GPIOs: four I/Os support PWM and four I/Os support double

PWM features.

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