ST2100 datasheet(10/39 Pages) STMICROELECTRONICS

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Architecture description

ST2100

10/39

DocID025777 Rev 1

3.1

CPU subsystem



ARM926EJ-S™ running at 333 MHz with:

–

MMU

–

16 Kbyte of instruction cache

–

16 Kbyte of data cache

–

32 Kbyte of instruction “Tightly Coupled Memory“ (TCM)

–

16 Kbyte of data “Tightly Coupled Memory” (TCM)

–

AMBA bus interface

–JTAG

–

ETM9 (Embedded Trace Macrocell) for debug, medium size version



Interrupt controller managing sources which are prioritized and vectorized

3.2

System bus

The system bus structure allows different subsystem data flows to be executed in parallel

improving the core platform efficiency.

High performance master agents are directly interconnected with the memory controller

reducing the memory access latency. The overall memory bandwidth assigned to each

master port can be programmed and optimized through an internal efficient weighted round-

robin arbitration mechanism.

Table 2 shows the system bus scheme and Table 3 is the key to its contents.

Table 2. System bus connectivity

Targets

(slave ports)

MP SDRAM

Low speed

Application

Basic

High speed

Expi

Table 3. Key to system bus connectivity matrix

Format

Definition

Grey box

No connection exists between target and initiator

A connection exists between target and initiator

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