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PAC5250 Datasheet(PDF) 41 Page - Active-Semi, Inc |
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PAC5250 Datasheet(HTML) 41 Page - Active-Semi, Inc |
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41 / 70 page  PAC5250 Power Application Controller 12.3.6. Gate Driver Fault Protection The ASPD incorporates a configurable fault protection mechanism using two protection event signals from the Configurable Analog Front End (CAFE), designated as protection event 1 (PR1) and protection event 2 (PR2) signals. The DRL0/DRL1/DRL2 drivers are designated as low-side group 1, and the DRL3/DRL4/DRL5 gate drivers are designed as low-side group 2. The DXH0/DXH1/DXH2 ultra-high-voltage gate drivers are designated as high-side group 1. The PR1 signal from the CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings. The PR2 signal from the CAFE can be used to disable low-side group 2, high-side group 2, or both depending on the PR2 mask bit settings. ENHS2 (high-side group 2 control output) pin is provided for enabling external power drivers with fault protection. - 41 - Rev 1.6‒January 28, 2016 |
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