PEB2255 datasheet(51/374 Pages) INFINEON

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PEB 2255

FALC-LH V1.3

Functional Description E1/T1/J1

Data Sheet

2000-07

Figure 9

Interrupt Status Registers

Each interrupt indication of registers ISR0…3,5 can be selectively masked by setting the

corresponding bit in the corresponding mask registers IMR0…3,5. If the interrupt status

bits are masked they neither generate an interrupt at INT nor are they visible in

ISR0 … 3,5.

GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending

interrupts. After the FALC

®-LH has requested an interrupt by activating its INT pin, the

CPU should first read the Global Interrupt Status register GIS to identify the requesting

interrupt source register. After reading the assigned interrupt status registers

ISR0...ISR3 and ISR5, the pointer in register GIS is cleared or updated if another

interrupt requires service.

If all pending interrupts are acknowledged by reading (GIS is reset), pin INT goes

inactive.

Updating of interrupt status registers ISR0 … 3,5 and GIS is only prohibited during read

access.

Masked Interrupts Visible in Status Registers

• The Global Interrupt Status register (GIS) indicates those interrupt status registers

with active interrupt indications (GIS.ISR0...3,5).

• An additional mode can be selected via bit IPC.VIS.

• In this mode, masked interrupt status bits neither generate an interrupt at pin INT nor

are they visible in GIS, but are displayed in the respective interrupt status

This mode is useful when some interrupt status bits are to be polled in the individual

interrupt status registers.

ITS09740

ISR0

ISR1

ISR3 ISR2

GIS

ISR3

IMR3

IMR0

ISR0

ISR1

IMR1

IMR2

ISR2

ISR5

IMR5

ISR5

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