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PEB2255 Datasheet(PDF) 54 Page - Infineon Technologies AG |
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PEB2255 Datasheet(HTML) 54 Page - Infineon Technologies AG |
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54 / 374 page ![]() PEB 2255 FALC-LH V1.3 Functional Description E1 Data Sheet 54 2000-07 4 Functional Description E1 4.1 Receive Path in E1 Mode Figure 11 Receive Clock System (E1) Receive Line Interface For data input, three different data types are supported: • Ternary coded signals received at multifunction ports RL1 and RL2 from a -10 dB (short haul, LIM0.EQON = 0) or -43 dB (long haul, LIM0.EQON = 1) ternary interface. The ternary interface is selected if LIM1.DRS is reset. • Digital dual rail signals received on ports RDIP and RDIN. The dual rail interface is selected if LIM1.DRS and FMR0.RC1 is set. • Unipolar data on port ROID received from a fiber optical interface. The optical interface is selected if LIM1.DRS is set and FMR0.RC1 is reset. Alternatively the optical interface can be switched to pin 68 (XMFB/XOID) and pin 80 (ROID) by setting bit LOOP.SPN. Equalizer Clock & Data Recovery DPLL Line Decoder Alarm Detector Analog LOS Detector RDATA RCLK DCO-R PD Osc. SYNC XTAL1 16.384 MHz RL1/RDIP/ROID RL2/RDIN/RCLKI F0057 |
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