PEB2255 datasheet(13/374 Pages) INFINEON

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PEB 2255

FALC-LH V1.3

List of Figures

Page

Data Sheet

2000-07

Figure 1

Logic Symbol ...... ..... ...... ..... ...... ...... ..... ..... 21

Figure 2

Multiple E1/T1/J1 Link over Frame Relay ...... ...... ..... ..... 22

Figure 3

8 Channel E1/T1/J1 Interface to the ATM Layer . ...... ..... ..... 23

Figure 4

Multiple FALC Clocking Options . . ..... ...... ...... ..... ..... 23

Figure 5

Pin Configuration ... ..... ...... ..... ...... ...... ..... ..... 24

Figure 6

Block Diagram ..... ..... ...... ..... ...... ...... ..... ..... 46

Figure 7

FIFO Word Access (Intel Mode) . . ..... ...... ...... ..... ..... 49

Figure 8

FIFO Word Access (Motorola Mode) .... ...... ...... ..... ..... 50

Figure 9

Interrupt Status Registers . ...... ..... ...... ...... ..... ..... 51

Figure 10

Block Diagram of Test Access Port and Boundary Scan . ..... ..... 53

Figure 11

Receive Clock System (E1) ...... ..... ...... ...... ..... ..... 54

Figure 12

ReceiverConfiguration (E1)...... ..... ...... ...... ..... ..... 56

Figure 13

JitterAttenuation Performance (E1)..... ...... ...... ..... ..... 59

Figure 14

JitterTolerance (E1) ..... ...... ..... ...... ...... ..... ..... 60

Figure 15

TransmitClock System (E1) ..... ..... ...... ...... ..... ..... 62

Figure 16

The Receive Elastic Buffer as Circularly Organized Memory . . ..... 65

Figure 17

2.048 MHz Receive Signaling Highway (E1) .... ...... ..... ..... 68

Figure 18

System Interface (E1) .... ...... ..... ...... ...... ..... ..... 70

Figure 19

Receive System Interface Clocking (E1). ...... ...... ..... ..... 71

Figure 20

Transmit System Interface Clocking: 2.048 MHz (E1) ... ..... ..... 74

Figure 21

Transmit System Interface Clocking: 8.192MHz/4.096 Mbit/s (E1)... 75

Figure 22

2.048 MHz TransmitSignaling Highway (E1) ... ...... ..... ..... 77

Figure 23

Transmitter Configuration (E1).... ..... ...... ...... ..... ..... 79

Figure 24

TransmitLine MonitorConfiguration (E1) ...... ...... ..... ..... 81

Figure 25

Data Flow in Transparent Mode ... ..... ...... ...... ..... ..... 84

Figure 26

CRC4 Multiframe AlignmentRecovery Algorithms ..... ..... ..... 92

Figure 27

Remote Loop (E1) . . ..... ...... ..... ...... ...... ..... ..... 97

Figure 28

Payload Loop (E1) . . ..... ...... ..... ...... ...... ..... ..... 98

Figure 29

Local Loop (E1) .... ..... ...... ..... ...... ...... ..... ..... 99

Figure 30

Single Channel Loopback (E1) . . . ..... ...... ...... ..... .... 100

Figure 31

Receive Clock System (T1/J1).... ..... ...... ...... ..... .... 102

Figure 32

ReceiverConfiguration (T1/J1) ... ..... ...... ...... ..... .... 104

Figure 33

JitterAttenuation Performance (T1/J1) .. ...... ...... ..... .... 107

Figure 34

JitterTolerance (T1/J1) ... ...... ..... ...... ...... ..... .... 108

Figure 35

TransmitClock System (T1/J1) ... ..... ...... ...... ..... .... 110

Figure 36

The Receive Elastic Buffer as Circularly Organized Memory . . .... 113

Figure 37

System Interface (T1/J1) . . ...... ..... ...... ...... ..... .... 118

Figure 38

Receive System Interface Clocking (T1/J1) ..... ...... ..... .... 119

Figure 39

2.048 Mbit/s Receive Signaling Highway (T1/J1) ...... ..... .... 120

Figure 401.544 Mbit/s Receive Signaling Highway (T1/J1) ...... ..... .... 120

Figure 41

Receive FS/DL Bits in Time Slot0 on RDO (T1/J1)..... ..... .... 122

Figure 42

Transmit System Interface Clocking: 1.544 MHz (T1/J1). ..... .... 124

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