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PEB20321 Datasheet(PDF) 91 Page - Infineon Technologies AG |
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PEB20321 Datasheet(HTML) 91 Page - Infineon Technologies AG |
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91 / 366 page ![]() PEB 20321 PEF 20321 Detailed Protocol Description Data Sheet 91 2001-02-14 ERR: issued if one of the following error conditions has occurred: – FCS was incorrect – the bit length was greater than MFL – the frame was stopped by 7FH – the frame could only be partly stored because of internal buffer overflow of RB – a fast receive abort channel command was issued – a receive abort channel command was detected during reception of a frame – a frame could only be partly transferred to the shared memory because of a receive descriptor with HOLD bit set (maskable by RE in the channel spec.) FO: issued if due to inaccessibility of internal buffer RB – one ore more complete frames have been lost – one ore more changes of interframe time-fill state were lost (maskable by RE in the channel spec.) Note that all receive interrupts are maskable by setting the bit field RID in MODE1 register. Example: HDLC channel with CS = 1 (FCS transferred to shared memory) INV = 0 (no inversion) CRC = 1 (CRC 32) TRV = 00 (required as unused in HDLC mode) FA = x (irrelevant in Rx direction) MODE = 11 (HDLC) IFTF = x (irrelevant in Rx direction) Big Endian Data Format Channel No. 1D MFL = 10 |
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