GS1660 datasheet(30/82 Pages) SEMTECH

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GS1660 HD/SD SDI Receiver

Data Sheet

53834 - 2

September 2012

30 of 82

4.8 Parallel Data Outputs

The parallel data outputs are aligned to the rising edge of the PCLK.

4.8.1 Parallel Data Bus Buffers

The parallel data bus, status signal outputs and control signal input pins are all

connected to high-impedance buffers.

The device supports 1.8 or 3.3V (LVTTL and LVCMOS levels) supplied at the IO_VDD and

IO_GND pins.

All output buffers (including the PCLK output), are set to high-impedance in Reset mode

(RESET_TRST = LOW).

Figure 4-2: PCLK to Data and Control Signal Output Timing - SDR Mode 1

toh

tr/tf (min)

Cload

tod

tr/tf (max)

Cload

toh

tr/tf (min)

Cload

tod

tr/tf (max)

Cload

dbus

1.000ns

0.400ns

3.700ns

1.400ns

1.000ns

0.400ns

3.700ns

1.400ns

stat

1.000ns

0.500ns

4.100ns

1.600ns

1.000ns

0.400ns

4.400ns

1.500ns

10bHD Mode

3.3V

1.8V

6 pF

15 pF

6 pF

15 pF

I/O Timing Specs:

DBUS[19:10]

PCLK_OUT

Cr0

6.734ns (HD 10-bit)

37.037ns (SD 10-bit)

20%

80%

20%

80%

Cb1

10-bit SDR Mode:

toh

tod

toh

tr/tf (min)

Cload

tod

tr/tf (max)

Cload

toh

tr/tf (min)

Cload

tod

tr/tf (max)

Cload

dbus

19.400ns

0.400ns

22.200ns 1.400ns

19.400ns

0.400ns

22.200ns

1.400ns

stat

19.400ns

0.500ns

22.200ns 1.600ns

19.400ns

0.400ns

22.200ns

1.500ns

10bSD Mode

3.3V

1.8V

6 pF

15 pF

6 pF

15 pF

GS1660 Datasheet(PDF) 30 Page - Semtech Corporation

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