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S3C72P9 Datasheet(PDF) 89 Page - Samsung semiconductor |
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S3C72P9 Datasheet(HTML) 89 Page - Samsung semiconductor |
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89 / 225 page ![]() S3C72P9/P72P9 (Preliminary Spec) MEMORY MAP 4-39 TMOD1 — Timer/Counter 1 Mode Register T/C FA1H, FA0H Bit 3 2 1 0 3 2 1 0 Identifier "0" .6 .5 .4 .3 .2 "0" "0" RESET RESET Value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Bit Addressing 8 8 8 8 1/8 8 8 8 TMOD1.7 Bit 7 0 Always logic zero TMOD1.6 – .4 Timer/Counter 1 Input Clock Selection Bit 0 0 0 External clock input at TCL1 pin on rising edge 0 0 1 External clock input at TCL1 pin on falling edge 1 0 0 fxx/210 (4.09 kHz) 1 0 1 fxx/28 (16.4 kHz) 1 1 0 fxx/26 (65.5 kHz) 1 1 1 fxx/24 (262 kHz) NOTE: “fxx” is selected system clock of 4.19 MHz TMOD1.3 Clear Counter and Resume Counting Control Bit 1 Clear TCNT1, IRQT1, and TOL1 and resume counting immediately (This bit is cleared automatically when counting starts.) TMOD1.2 Enable/Disable Timer/Counter 1 Bit 0 Disable timer/counter 1; retain TCNT1 contents 1 Enable timer/counter 1 TMOD1.1 Bit 1 0 Always logic zero TMOD1.0 Bit 0 0 Always logic zero |
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