PE43713 datasheet(2/31 Pages) PSEMI

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PE43713

UltraCMOS® RF Digital Step Attenuator

Page 2

DOC-49614-1 – (3/2015)

www.psemi.com

Peregrine’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an

innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and

integration of conventional CMOS.

Optional External V

Control

For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in Table 2.

When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage

generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally

to bypass the internal negative voltage generator.

Absolute Maximum Ratings

Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be

restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for

extended periods may reduce reliability.

ESD Precautions

When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.

Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to

avoid exceeding the rating specified in Table 1.

Latch-up Immunity

Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.

Table 1 • Absolute Maximum Ratings for PE43713

Parameter/Condition

Min

Max

Unit

Supply voltage, VDD

–0.3

5.5

Digital input voltage

–0.3

3.6

RF input power, 50

Ω

9 kHz–48 MHz

>48 MHz–6 GHz

Figure 5

+31

dBm

Storage temperature range

–65

+150

°C

ESD voltage HBM, all pins(1)

3000

ESD voltage CDM, all pins(2)

1000

Notes:

1) Human body model (MIL–STD 883 Method 3015).

2) Charged device model (JEDEC JESD22–C101).

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