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SPX2967 Datasheet(PDF) 2 Page - Sipex Corporation |
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SPX2967 Datasheet(HTML) 2 Page - Sipex Corporation |
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2 / 12 page ![]() 2 Date: 8/23/04 SPX2967 400mA Low Dropout Voltage Regulator © Copyright 2004 Sipex Corporation APPLICATIONS INFORMATION The IC regulates an input voltage V I in the range of 5.5 V < VI <40 V to a nominal output voltage of V Q= 5.0V. A reset signal is generated for an output voltage of VQ < VRT (typ. 4.5V). The reset delay can be set with an external capacitor. The device has two logic inputs. A voltage of V E2 >4.0V given to the E2-pin (e.g. by ignition) turns the device on. Depending on the voltage on pin E6 the IC may be hold in active-state even if V E2 goes down to low level. This makes it simple to implement a self-holding circuit without external components. When the device is turned off, the output voltage drops to 0V and current consumption tends towards 0 µA. DESIGN NOTES FOR EXTERNAL COMPONENTS The input capacitor C I is necessary for compensation of line influences. The resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approxi- mately 1Ω in series with C I . The output capacitor is necessary for the stability of the regulating circuit. Stability is guaranteed at values of ≥ 22µF and an ESR of less than 3Ω within the operating temperature range. The control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents and over- saturation of the power element. The reset output RO is in high state if the voltage on the delay capacitor C D greater than or equal to V UD. The delay capacitance CD is charged with the current ID for output voltages greater than the reset threshold V RT. If the output voltage gets lower than VRT a fast discharge of the delay capacitor C D sets in and as soon as VCD gets lower than VLD the reset output RO is set to low-level. The reset delay can be set within wide range by dimensioning the capacitance of the external capacitor. CIRCUIT DESCRIPTION PIN DESCRIPTION N I P R E B M U N E M A N N I PN O I T P I R C S E D 1I ; t u p n I . r o t i c a p a c c i m a r e c a h t i w C I e h t t a y l t c e r i d D N G o t k c o l B 22 E ; t i b i h n I n w o d ll u p l a n r e t n i ; n i p s i h t n o l a n g i s h g i H y b n o d e n r u t s i e c i v e D Ω k 0 0 1 f o r o t s i s e r 3O R ; t u p t u O t e s e R k 0 3 a a i v Q o t d e k n il y ll a n r e t n i s i t u p t u o r o t c e ll o c - n e p o e h T . d e d e e n t o n f i n e p o t i p e e K . r o t s i s e r Ω 4D N G ; d n u o r G p i h c f o r a e r o t d e t c e n n o c 5D ; y a l e D t e s e R y a l e d g n i t t e s r o f D N G o t r o t i c a p a c a i v t c e n n o c 66 E ; d l o H e g a t l o v t u p t u o o t d e t c e n n o c s i t u p n i s i h t ; n o i t c n u f r o f e l b a t h t u r t e e s Ω k 0 5 f o r o t s i s e r p u ll u p a a i v 7Q ; t u p t u O V 5 Ω 3 < R S E , r o t i c a p a c F µ 2 2 h t i w D N G o t k c o l b |
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